Analyzing the Signal Integrity of a DDR2 Memory Interface with HSPICE
时间：Tuesday, February 13, 2007 11:00 am PT/2:00 pm ET
如果我没有算错的话：
2007年2月13日 星期三 北京时间：3:00 am (计算请参见我的上一篇内容)
简介：
For years designers around the world have trusted HSPICE for their signal integrity simulation needs. For video memory and many other applications, increases in chip and board speeds over the last few years have created significant and widespread demand for accurate signal integrity analysis. This tutorial walks through the setup, simulation and analysis of a Synopsys DDR2 memory interface highlighting HSPICE’s signal integrity analysis features.
Who should attend
Design engineers, CAD engineers, and engineering management supporting board and chip level signal integrity design and verification.
What you will learn
* Using HSPICE to perform signal integrity analysis on a DDR2 Memory Interface.
* Modeling frequency dependent characteristics in time domain.
* Creating signal integrity test benches.
* Interpreting eye diagrams for signal integrity.