十二、 Flash存储器

#define FCTL1              (0x0128)  /* FLASH Control 1 */

#define FCTL2             (0x012A)  /* FLASH Control 2 */

#define FCTL3              (0x012C)  /* FLASH Control 3 */

#define FRKEY               (0x9600)  /* Flash key returned by read */

#define FWKEY               (0xA500)  /* Flash key for write */

#define FXKEY               (0x3300)  /* for use with XOR instruction */

#define ERASE               (0x0002)  /* Enable bit for Flash segment erase */

#define MERAS               (0x0004)  /* Enable bit for Flash mass erase */

#define WRT                 (0x0040)  /* Enable bit for Flash write */

#define BLKWRT              (0x0080)  /* Enable bit for Flash segment write */

#define SEGWRT              (0x0080)  /* old definition */ /* Enable bit for Flash segment write */

#define FN0                 (0x0001)  /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */

#define FN1                 (0x0002)  /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */

#define FN2                 (0x0004) 

#define FN3                 (0x0008) 

#define FN4                 (0x0010)

#define FN5                 (0x0020)

#define FSSEL0              (0x0040)  /* Flash clock select 0 */        /* to distinguish from USART SSELx */

#define FSSEL1              (0x0080)  /* Flash clock select 1 */

#define FSSEL_0             (0x0000)  /* Flash clock select: 0 - ACLK */

#define FSSEL_1             (0x0040)  /* Flash clock select: 1 - MCLK */

#define FSSEL_2             (0x0080)  /* Flash clock select: 2 - SMCLK */

#define FSSEL_3             (0x00C0)  /* Flash clock select: 3 - SMCLK */

#define BUSY                (0x0001)  /* Flash busy: 1 */

#define KEYV                (0x0002)  /* Flash Key violation flag */

#define ACCVIFG             (0x0004)  /* Flash Access violation flag */

#define WAIT                (0x0008)  /* Wait flag for segment write */

#define LOCK                (0x0010)  /* Lock bit: 1 - Flash is locked (read only) */

#define EMEX                (0x0020)  /* Flash Emergency Exit */

十三、比较器

#define CACTL1             (0x0059)  /* Comparator A Control 1 */

#define CACTL2             (0x005A)  /* Comparator A Control 2 */

#define CAPD               (0x005B)  /* Comparator A Port Disable */

#define CAIFG               (0x01)    /* Comp. A Interrupt Flag */

#define CAIE                (0x02)    /* Comp. A Interrupt Enable */

#define CAIES               (0x04)    /* Comp. A Int. Edge Select: 0:rising / 1:falling */

#define CAON                (0x08)    /* Comp. A enable */

#define CAREF0              (0x10)    /* Comp. A Internal Reference Select 0 */

#define CAREF1              (0x20)    /* Comp. A Internal Reference Select 1 */

#define CARSEL              (0x40)    /* Comp. A Internal Reference Enable */

#define CAEX                (0x80)    /* Comp. A Exchange Inputs */

#define CAREF_0             (0x00)    /* Comp. A Int. Ref. Select 0 : Off */

#define CAREF_1             (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */

#define CAREF_2             (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */

#define CAREF_3             (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/

#define CAOUT               (0x01)    /* Comp. A Output */

#define CAF                 (0x02)    /* Comp. A Enable Output Filter */

#define P2CA0               (0x04)    /* Comp. A Connect External Signal to CA0 : 1 */

#define P2CA1               (0x08)    /* Comp. A Connect External Signal to CA1 : 1 */

#define CACTL24             (0x10)

#define CACTL25             (0x20)

#define CACTL26             (0x40)

#define CACTL27             (0x80)

#define CAPD0               (0x01)    /* Comp. A Disable Input Buffer of Port Register .0 */

#define CAPD1               (0x02)    /* Comp. A Disable Input Buffer of Port Register .1 */

#define CAPD2               (0x04)    /* Comp. A Disable Input Buffer of Port Register .2 */

#define CAPD3               (0x08)    /* Comp. A Disable Input Buffer of Port Register .3 */

#define CAPD4               (0x10)    /* Comp. A Disable Input Buffer of Port Register .4 */

#define CAPD5               (0x20)    /* Comp. A Disable Input Buffer of Port Register .5 */

#define CAPD6               (0x40)    /* Comp. A Disable Input Buffer of Port Register .6 */

#define CAPD7               (0x80)    /* Comp. A Disable Input Buffer of Port Register .7 */

十四、中断向量

#define BASICTIMER_VECTOR       (0 * 2u)  /* 0xFFE0 Basic Timer */

#define PORT2_VECTOR             (1 * 2u)  /* 0xFFE2 Port 2 */

#define PORT1_VECTOR             (4 * 2u)  /* 0xFFE8 Port 1 */

#define TIMERA1_VECTOR          (5 * 2u)  /* 0xFFEA Timer A CC1-2, TA */

#define TIMERA0_VECTOR           (6 * 2u)  /* 0xFFEC Timer A CC0 */

#define WDT_VECTOR              (10 * 2u) /* 0xFFF4 Watchdog Timer */

#define COMPARATORA_VECTOR  (11 * 2u) /* 0xFFF6 Comparator A */

#define NMI_VECTOR               (14 * 2u) /* 0xFFFC Non-maskable */

#define RESET_VECTOR             (15 * 2u) /* 0xFFFE Reset [Highest Priority] */

十一、  Timer A3

1）寄存器：

TAIV        (0x012E)  中断向量寄存器

TACTL       (0x0160)  控制寄存器

CCTL0       (0x0162)  捕获比较控制寄存器0

CCTL1       (0x0164)  捕获比较控制寄存器1

CCTL2       (0x0166)  捕获比较控制寄存器2

TAR          (0x0170)  寄存器

CCR0        (0x0172)  捕获比较寄存器0

CCR1        (0x0174)  捕获比较寄存器1

CCR2        (0x0176)  捕获比较寄存器2

2）TACTL中的各位                                SSEL1           SSEL0           输入信号

TASSEL2    (0x0400)  未用                   0                   0                   TACLK（特定的外部信号）

TASSEL1    (0x0200)   时钟选择          0                   1                   ACLK    

TASSEL0    (0x0100)   时钟选择         1                   0                MCLK

ID1         (0x0080)   输入信号分频： 00 直通； 01：2分频

ID0         (0x0040)   与ID1一起：   10 4分频    11：8分频

MC1        (0x0020)   两位一起：00 停止；01：增记数到CCR0；

MC0        (0x0010)   模式控制：10 连续增记数，  11 增记数到CCR0，减记数到0H；

TACLR      (0x0004)  定时器清除位

TAIE        (0x0002)  中断允许

TAIFG      (0x0001)   定时器溢出标志

#define MC_0                (0*0x10u)  /* Timer A mode control: 0 - Stop */

#define MC_1                (1*0x10u)  /* Timer A mode control: 1 - Up to CCR0 */

#define MC_2                (2*0x10u)  /* Timer A mode control: 2 - Continous up */

#define MC_3                (3*0x10u)  /* Timer A mode control: 3 - Up/Down */

#define ID_0                (0*0x40u)  /* Timer A input divider: 0 - /1 */

#define ID_1                (1*0x40u)  /* Timer A input divider: 1 - /2 */

#define ID_2                (2*0x40u)  /* Timer A input divider: 2 - /4 */

#define ID_3                (3*0x40u)  /* Timer A input divider: 3 - /8 */

#define TASSEL_0            (0*0x100u) /* Timer A clock source select: 0 - TACLK */

#define TASSEL_1            (1*0x100u) /* Timer A clock source select: 1 - ACLK  */

#define TASSEL_2            (2*0x100u) /* Timer A clock source select: 2 - SMCLK */

#define TASSEL_3            (3*0x100u) /* Timer A clock source select: 3 - INCLK */

3）捕获比较控制寄存器 CCTLX 对应的位

CM1       (0x8000)   00 禁止                    01 上升沿捕获

CM0       (0x4000)   10 下降沿捕获          11  上升沿与下降沿都捕获

CCIS1        (0x2000)   CCIS0和CCIS1输入选择  00 选择CCIXA；

CCIS0        (0x1000)                                            01 选择CCIXB， 10 GND   11 VCC

SCS          (0x0800)   0异步捕获  1 同步捕获

SCCI         (0x0400)   捕获比较输入信号与比较输出EQUX同步

CAP          (0x0100)   0 比较模式      1 捕获模式

OUTMOD2    (0x0080)   

OUTMOD1    (0x0040)   

OUTMOD0    (0x0020)   

CCIE         (0x0010)   1 允许中断      0 禁止中断

CCI          (0x0008)   捕获/比较输入信号选择

OUT     （0x0004)   

COV          (0x0002)   

CCIFG        (0x0001)   中断标志（与CCRX有关）

#define OUTMOD_0            (0*0x20u)  /* PWM output mode: 0 - output only */

#define OUTMOD_1            (1*0x20u)  /* PWM output mode: 1 - set */

#define OUTMOD_2            (2*0x20u)  /* PWM output mode: 2 - PWM toggle/reset */

#define OUTMOD_3            (3*0x20u)  /* PWM output mode: 3 - PWM set/reset */

#define OUTMOD_4            (4*0x20u)  /* PWM output mode: 4 - toggle */

#define OUTMOD_5            (5*0x20u)  /* PWM output mode: 5 - Reset */

#define OUTMOD_6            (6*0x20u)  /* PWM output mode: 6 - PWM toggle/set */

#define OUTMOD_7            (7*0x20u)  /* PWM output mode: 7 - PWM reset/set */

#define CCIS_0              (0*0x1000u) /* Capture input select: 0 - CCIxA */

#define CCIS_1              (1*0x1000u) /* Capture input select: 1 - CCIxB */

#define CCIS_2              (2*0x1000u) /* Capture input select: 2 - GND */

#define CCIS_3              (3*0x1000u) /* Capture input select: 3 - Vcc */

#define CM_0                (0*0x4000u) /* Capture mode: 0 - disabled */

#define CM_1                (1*0x4000u) /* Capture mode: 1 - pos. edge */

#define CM_2                (2*0x4000u) /* Capture mode: 1 - neg. edge */

#define CM_3                (3*0x4000u) /* Capture mode: 1 - both edges */

4）TAIV  中断向量寄存器

                    中断源             缩写                      

最高中断优先级： 捕获/比较0                CCIFG0                       N。A

                             捕获/比较1                CCIFG1                       2

捕获/比较2                CCIFG2                       4

捕获/比较3                CCIFG3                       6

捕获/比较4                CCIFG4                       8

                            定时器益出                TAIFG                         10

最低优先级：    保留

注意：

   TAIFG和CCIFG与其他四个捕获/比较寄存器CCRX相关，如果有任何一个中断允许位置位（CCIEX或TAIE），并且相应的中断标志也置位，则会产生一个中断请求，结合成一个中断向量，在TAIV中可读出。在PC读取TAIV中断向量后，CCIFGX与TAIFG自动复位。

八、系统时钟FLL+  （ SYSTEM CLOCK, FLL+ (x41x) ）

1）、相关的寄存器

SCFI0、SCFI1     ：系统时钟频率积分器

       SCFQCTL            ：系统时钟频率控制寄存器

（1）系统时钟频率积分器0 ： SCFI0       (0x0050) 

#define FN_2        (0x04)    /* fDCOCLK =   1.4-12MHz*/

#define FN_3       (0x08)    /* fDCOCLK =   2.2-17Mhz*/

#define FN_4       (0x10)    /* fDCOCLK =   3.2-25Mhz*/

#define FN_8       (0x20)    /* fDCOCLK =     5-40Mhz*/

#define FLLD0      (0x40)    /* Loop Divider Bit : 0 */

#define FLLD1   (0x80)    /* Loop Divider Bit : 1 */

#define FLLD_1     (0x00)    /* Multiply Selected Loop Freq. By 1 */

#define FLLD_2    (0x40)    /* Multiply Selected Loop Freq. By 2 */

#define FLLD_4  (0x80)    /* Multiply Selected Loop Freq. By 4 */

#define FLLD_8  (0xC0)    /* Multiply Selected Loop Freq. By 8 */

（2）系统时钟频率积分器1 ：