EDIF - Electronic Design Interchange Format
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EDIF was an attempt to solve the problem stemmed from considerable competition among companies in electronic design automation (EDA) industry. These companies produced their own electronic design databases
which were highly proprietary. When customers needed to transfer data
from one system to another, it was necessary to write translators from
one format to other. As the number of formats (N) multiplied, the translator issue became an N-squared problem.
EDIF originated from a discussion of three men, who envisioned a
common, neutral format from which all the other formats could be
derived, and began work on this neutral format. In November 1983 this
effort grew into the EDIF Steering Committee, consisting of
representatives of Daisy Systems, Mentor Graphics, Motorola, National Semiconductor, Tektronix, Texas Instruments and the University of California, Berkeley.
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EDIF 分为EDIF netlist和EDIF schematic. EDIF netlist是描述电路网表，在Tanner的L-edit里面可以作为数字电路Place and Route的一个输入文件，而EDIF schematic 则是描述电路图的。
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就是一个网表文件，synplify综合后会生成这样一个网表文件，当然其他的工具也可以。edif网表文件可以用来仿真，也可以用来布线。
muxpusII可接直接调入这一网表文件，进行fitter……
-------------------ALTERA官方网站-------------------------
EDIF Input File (.edf) Definition
An
EDIF version 2 0 0 netlist file (with the extension (.edf), generated
by any standard EDIF netlist writer. The Quartus II software also
supports EDIF Input files with the extensions (.edif) or (.edn).
When
you compile an EDIF Input File, the Compiler uses one or more Library
Mapping Files (.lmf) to map cells in an EDIF Input File to
corresponding Quartus II logic functions, including Library of
Parameterized Modules (LPM) functions, as well as to user-defined
functions.
All logic functions in an EDIF Input File must be
mapped to the Quartus II software logic functions in a Library Mapping
File (.lmf). If you wish to use a function that is not mapped in a
Altera-provided LMF, you must create a customized LMF. You can map EDIF
cells to Altera-provided functions or to any design file created with
the Quartus II software.
The Compiler processes EDIF Input Files
automatically, generating a Compiler Netlist Extractor (.cnf) file for
every cell in an EDIF Input File. You can also specify EDIF Input
settings to help the Compiler interpret EDIF Input Files by specifying
optional LMFs and non-default VCC and GND signal names.
A single
EDIF Input File can be used to define all logic in a project, or can be
incorporated at any hierarchy level in a hierarchical project.
The
Quartus II software automatically creates a Block Symbol File (.bsf)
that represents an EDIF Input File when you open the file in the Text
Editor and create the default symbol for the current file. This symbol
and the logic it represents can be incorporated into a Block Design
File (.bdf).
You can also use EDIF Input File logic in an AHDL
Text Design File (.tdf) by including a Function Prototype and inserting
an instance of the function into the TDF.
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