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Verilog pipeline 加法器
Pipeline：如果直接 {cout,sum}=ina+inb+cin; 构成一个并行的加法器，会消耗较多资源。而pipeline只是加了一些中间寄存器，把复杂的8位运算分成4个2位运算，求第一个结果需要延时4个周期，但是后面的结果就只需要一个周期，而且每级运算结构简单，所以可以高频率运行。
王金明书中的程序搞了很久，就是不正确，还好Lotus找到了错误的原因，但是不知道为什么会发生错误？
Lotus更改正确的程序：
module addpipeline(cout,sum,ina,inb,cin,clk);
input [7:0]ina,inb;
input cin,clk;
output [7:0]sum;
output cout;
reg firstco,secondco,thirdco;
reg cout;
reg [7:0] sum;
reg [1:0]firsts,thirda,thirdb;
reg [5:0]firsta,firstb,thirds;
reg [3:0]seconda,secondb,seconds;
always @(posedge clk)
begin
{firstco,firsts}<=ina[1:0]+inb[1:0]+cin;
firsta<=ina[7:2];
firstb<=inb[7:2];
end
always @(posedge clk)
begin
seconds[1:0]<=firsts;
{secondco,seconds[3:2]}<=firsta[1:0]+firstb[1:0]+firstco;
seconda<=firsta[5:2];
secondb<=firstb[5:2];
end
always @(posedge clk)
begin
thirds[3:0]<=seconds;
{thirdco,thirds[5:4]}<=seconda[1:0]+secondb[1:0]+secondco;
thirda<=seconda[3:2];
thirdb<=secondb[3:2];
end
always @(posedge clk)
begin
sum[5:0]<=thirds;
{cout,sum[7:6]}<=thirda[1:0]+thirdb[1:0]+thirdco;
end
endmodule
// 去掉了temp变量，使延时少了1个周期。
// 书中程序仿真总是进位为0，
把{secondco,seconds}<={firsta[1:0]+firstb[1:0]+firstco,firsts};
改为seconds[1:0]<=firsts;
{secondco,seconds[3:2]}<=firsta[1:0]+firstb[1:0]+firstco; 进位正确。
好像书中的这种拼接方式有误使得进位始终为0。
王金明书中的程序：
module pipeline(cout,sum,ina,inb,cin,clk);
output[7:0] sum;
output cout;
input cin,clk;
input [7:0] ina,inb;
reg[7:0] tempa,tempb,sum;
reg tempci,firstco,secondco,thirdco,cout;
reg[1:0] firsts,thirda,thirdb;
reg[3:0] seconds,seconda,secondb;
reg[5:0] firsta,firstb,thirds;
always@(posedge clk)
begin
tempa<=ina;tempb<=inb;tempci<=cin;
end
//firstco is the carry of the lowest 2 bit adding
//firsts is the summary of the lowest 2 bit adding
//firsta/firstb is the highest 6 bit of ina/inb
always@(posedge clk)
begin
{firstco,firsts}<=tempa[1:0]+tempb[1:0]+tempci; 这一句进位正确
firsta<=tempa[7:2];firstb<=tempb[7:2];
end
//seconds is the summary of the lowest 4 bit adding
//seconda/secondb is the highest 4 bit of ina/inb
always@(posedge clk)
begin
{secondco,seconds}<={firsta[1:0]+firstb[1:0]+firstco,firsts}; 进位错误
seconda<=firsta[5:2];secondb<=firstb[5:2];
end
//thirds is the summary of the lowest 6 bit adding
//thirda/thirdb is the highest 2 bit of ina/inb
always@(posedge clk)
begin
{thirdco,thirds}<={seconda[1:0]+secondb[1:0]+secondco,seconds};
thirda<=seconda[3:2]; thirdb<=secondb[3:2];
end
always@(posedge clk)
begin
{cout,sum}<={thirda[1:0]+thirdb[1:0]+thirdco,thirds};
end
endmodule
系统分类:
CPLD/FPGA | 用户分类:
Verilog | 来源:
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