GAL16V8的D触发器问题

原帖：http://bbs.21ic.com/club/bbs/list.asp?boardid=11&t=2851563

eric 发表于 2008-2-4 08:23 侃单片机 ←返回版面

楼主： 用PROTEL99SE的原理图方式编辑GAL16V8D的程序，如何加入锁存器?

最近用PROTEL99SE的原理图方式编辑GAL16V8D，弄个简单的74HC02功能，都很正常，又加了个锁存器，就编辑不过去了，在配置里选择了GAL16V8的很多模式都不行，很迷惑，请有经验的工程师看看，指点一二。

hotpower 发表于 2008-2-6 01:44 侃单片机 ←返回版面

2楼： 哈哈~~~GAL16V8有8个乘积项,刚好可以,11脚要加三态使能

1脚是时钟信号输入,不占乘积项,所以输出要由11脚三态控制. 你的电路是直通的,简单组合逻辑内部三态控制直通,D触发器需要外部11脚接高电平使能(记得好像是高电平)就变成直通的了. Cupl语言程序设计包 俺只会写代码~~~D触发器很好写,就是2分频.把"D=Q"变成"D.d=Q"即可. abel是用:=表示.   GAL16V8问题解答

hotpower 发表于 2008-2-6 04:04 侃单片机 ←返回版面

7楼： 哈哈~~~Q管脚看错了,应该在12脚~~~

Name        74HC02                                  ; Partno                                              ; Revision    V1.0                                       ; Date        2/6/08                                 ; Designer    HotPower                                ; Company     http://www.ednchina.com/blog/hotpower/ ; Assembly                                            ; Location                                            ; Device      g16v8                                   ; Format      j                                       ; /** Inputs  **/ Pin[1, 11]             = [clk, oe]; Pin[2..9]              = [A1, B1, A2, B2, A3, B3, A4, B4]; /** Outputs **/ Pin[19, 17, 15, 13]    = [C1, C2, C3, C4]; Pin[12]                = [Q];//改改很方便~~~ /** Logic Equations **/ !C1   = A1 # B1; !C2   = A2 # B2; !C3   = A3 # B3; !C4   = A4 # B4;   Q.d = B4;                                ______________                               |    74HC02    |                       clk x---|1           20|---x Vcc                        A1 x---|2           19|---x C1                        B1 x---|3           18|---x                        A2 x---|4           17|---x C2                        B2 x---|5           16|---x                        A3 x---|6           15|---x C3                        B3 x---|7           14|---x                        A4 x---|8           13|---x C4                        B4 x---|9           12|---x Q                       GND x---|10          11|---x oe                               |______________|

GAL16V8问题解答

hotpower 发表于 2008-1-27 02:33 侃单片机 ←返回版面

4楼： 楼主的运气不错,不过只能2个模块4路数字信号比较

搜索了74hc518没找到PDF文件... 由于GAL16V8系列只有8个乘积项,即乘积的和最多只能为8个,故'+'号只能出现7次. 所以电路必须接成P16V8S: A1 A2 A3 A4 A5 A6 A7 A8 B1 GND B2 B3 B4 B5 CS1 CS2 B6 B7 B8 VCC 程序应该写成:(你用的是FM软件???) /CS1=/A1*B1+A1*/B1+/A2*B2+A2*/B2+/A3*B3+A3*/B3+/A4*B4+A4*/B4 /CS2=/A5*B5+A5*/B5+/A6*B6+A6*/B6+/A7*B7+A7*/B7+/A8*B8+A8*/B8 这样就输出了2个信号,即有1路相等即输出低电平信号. 如果只能测试1个有效信号,就必须再/CS=/CS1*/CS2. 由于CS1和CS2不能线与,故需再加门电路或在CS1和CS2的输出 都加二极管IN4148后负极短接作为总输出/CS. 没用过FM软件,不知如何设置成'S型'. 对应的ABEL或CUPL语言写法: !CS1 = A1 $ B1 注意: A1 $ B1 = (A1 异或 B1) = !A1 & B1 # A1 & !B1      # A2 $ B2      # A3 $ B3      # A4 $ B4; !CS2 = A5 $ B5      # A6 $ B6      # A7 $ B7      # A8 $ B8;

hotpower 发表于 2008-1-27 02:49 侃单片机 ←返回版面

8楼： 看图识字~~~附74hc518.rar压缩包~~~

点击下载Protel 99 SE环境下的74hc518.rar压缩包

Cupl语言程序设计包

点击下载:Cupl语言程序设计包.rar 

83优先编码--Protel99SE自带CUPL语言设计

Name        PLDDesign7           ;
Partno                           ;
Revision    1                    ;
Date        3/13/02              ;
Designer    HotPower                  ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/13/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 11, 10, 20] = [ei, oe, GND, VCC];
Pin[2..9] = [d0..7];

/** Outputs **/
Pin[15..17] = [y0..2];
Pin[19] = gs;

/** Declarations and Intermediate Variables  **/
fld flds7 = [d7..0];
fld flds6 = [d6..0];
fld flds5 = [d5..0];
fld flds4 = [d4..0];
fld flds3 = [d3..0];
fld flds2 = [d2..0];
fld flds1 = [d1..0];
fld flds0 = [d0..0];

/** Logic Equations **/
y0 = (!ei & !oe) &
     ((d0 & !d1) #
     ( d0 & d1 & d2 & !d3) #
     ( d0 & d1 & d2 &  d3 & d4 & !d5) #
     ( d0 & d1 & d2 &  d3 & d4 &  d5 & d6 & !d7) #
     ( d0 & d1 & d2 &  d3 & d4 &  d5 & d6 &  d7));

y1 = (!ei & !oe) &
     ([d2..0]: 'b'011
   #  [d2..0]:& & !d3
   #  !d6 & [d5..0]:&
   #  [d7..0]: 'b'01111111
   #  [d7..0]: 'b'11111111); /** fids7:& **/

y2 = (!ei & !oe) &
     (flds4: 'b'01111    #
      flds5: 'b'011111   #
      flds6: 'b'0111111  #
      flds7: 'b'01111111 #
      flds7: 'b'11111111); /** fids7:& **/

gs = ei # oe # flds7:&;

IO地址译码设计--Protel99SE自带CUPL语言设计

Name        PLDDesign1           ;
Partno      1                    ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly    I/O read/write       ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin 2   =  a0;
Pin 3   =  a1;
Pin 4   =  a2;
Pin 5   =  a3;
Pin 6   =  a4;
Pin 7   =  a5;
Pin 8   =  a6;
Pin 9   =  a7;
Pin 12  =  iord;
Pin 13  =  iowr;

/** Outputs **/
Pin 19  =  buffen;

/** Declarations and Intermediate Variables  **/
field addr = [a7..0];
ioreq     = !iord # !iowr;

/** Logic Equations **/
!buffen     = ioreq & addr: [10..12];

电梯状态机设计--Protel99SE自带CUPL语言设计

Name        PLDDesign3            ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 11] = [clk, oe];
Pin[2, 3, 4] = [l1call, l2call, l3call];
Pin[5, 6, 7] = [arr1, arr2, arr3];
Pin[8, 9] = [emerg_stop, emerg_bell];

/** Outputs **/
Pin[12] = [door];
Pin[13, 14] = [motorup, motordn];
Pin[15, 16] = [f1_dira, f1_dirb];

Pin[17, 18] = [motionu, motiond];
Pin[19] = [bell];

/**  reduction level flags  **/
min door.d    = 2;
min f1_dira.d = 2;
min f1_dirb.d = 2;

/** internal node **/
up = !f1_dira;
dn =  f1_dira;

1floor = !f1_dira & !f1_dirb;
2floor = !1floor  & !3floor;
3floor =  f1_dira &  f1_dirb;

/** Logic Equations **/
motorup =  motionu & !emerg_stop
        & !f1_dira & (!arr2 # !arr3 # arr2 & !l2call);

motordn =  motiond & !emerg_stop
        & !f1_dira & (!arr1 # !arr2 # arr2 & !l2call);

   bell =  emerg_stop
        #  emerg_bell;

/** State Definitions **/
fld control = [!door, motionu, motiond, f1_dira, f1_dirb];

$define open1    'b'10000 /** 'h'10 **/
$define close1   'b'00000 /** 'h'00 **/
$define up1      'b'01000 /** 'h'08 **/
$define open2u   'b'10001 /** 'h'11 **/
$define open2d   'b'10010 /** 'h'12 **/
$define close2u  'b'00001 /** 'h'01 **/
$define close2d  'b'00010 /** 'h'02 **/
$define up2      'b'01001 /** 'h'09 **/
$define dn2      'b'00110 /** 'h'06 **/
$define open3    'b'10011 /** 'h'13 **/
$define close3   'b'00011 /** 'h'03 **/
$define dn3      'b'00111 /** 'h'07 **/

sequence control{

present open1:
        if l2call # l3call next up1;
        default next close1;

present close1:
        if l2call # l3call next up1;
        if l1call next open1;
        default next close1;

present up1:
        if arr2 & !l2call next up2;
        if arr2 &  l2call next open2u;
        default next up1;

present open2u:
        if l3call next up2;
        default next close2u;

present open2d:
        if l1call next dn2;
        default next close2d;

present close2u:
        if l3call next up2;
        if l2call next open2u;
        default next close2d;

present close2d:
        if l1call next dn2;
        if l2call next open2d;
        default next close2u;

present up2:
        if arr3 next open3;
        default next up2;

present dn2:
        if arr1 next open1;
        default next dn2;

present open3:
        if l1call # l2call next dn3;
        default next close3;

present close3:
        if l1call # l2call next dn3;
        if l3call next open3;
        default next close3;

present dn3:
        if arr2 & !l2call next dn2;
        if arr2 &  l2call next open2d;
        default next dn3;

}

全编码键盘设计--Protel99SE自带CUPL语言设计

Name        PLDDesign5            ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g20v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1,13] = [clk, oe];
Pin[12, 24] = [GND, VCC];
Pin[2..11, 14..17] = [k0..13];

/** Outputs **/
Pin[21..18] = [d3..0];

Pin[23, 22] = [rst, int];

/** Declarations and Intermediate Variables  **/
fld fldintd20 = [k13..0, k0];

fld fldint10  = [k1..0];
fld fldint20  = [k2..0];
fld fldint30  = [k3..0];
fld fldint40  = [k4..0];
fld fldint50  = [k5..0];
fld fldint60  = [k6..0];
fld fldint70  = [k7..0];
fld fldint80  = [k8..0];
fld fldint90  = [k9..0];
fld fldinta0  = [k10..0];
fld fldintb0  = [k11..0];
fld fldintc0  = [k12..0];
fld fldintd0  = [k13..0];
/** Logic Equations **/

!int = !rst
     # fldintd20: &;
d0.d = fldint10:  &
     # fldint30: 'b'0111
     # fldint50: 'b'011111
     # fldint70: 'b'01111111
     # fldint90: 'b'0111111111
     # fldintb0: 'b'011111111111
     # fldintd0: 'b'01111111111111;

d1.d = fldint20: 'b'011
     # fldint30: 'b'0111
     # fldint60: 'b'0111111
     # fldint70: 'b'01111111
     # fldinta0: 'b'01111111111
     # fldintb0: 'b'011111111111
     # fldintd0:  &;

d2.d = fldint40: 'b'01111
     # fldint50: 'b'011111
     # fldint60: 'b'0111111
     # fldint70: 'b'01111111
     # fldintc0: 'b'0111111111111
     # fldintd0: 'b'01111111111111
     # fldintd0:  &;

d3.d = fldint80: 'b'011111111
     # fldint90: 'b'0111111111
     # fldinta0: 'b'01111111111
     # fldintb0: 'b'011111111111
     # fldintc0: 'b'0111111111111
     # fldintd0: 'b'01111111111111
     # fldintd0:  &; /*'b'11111111111111*/

基本触发器设计--Protel99SE自带CUPL语言设计

Name        PLDDesign2           ;
Partno      2                    ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Rs Latch **/
Pin[2, 3, 19,18] = [s, r, qst, qsc];
/** T flip - flop **/
Pin[5, 17,16] = [t, qtt, qtc];
/** D flip - flop **/
Pin[6, 15,14] = [d, qdt, qdc];
/** JK flip - flop **/
Pin[7, 8, 13,12] = [j, k, qjt, qjc];
/** Control **/
Pin[1, 4, 9, 11] = [clk, pr, clr, oe];
/** Power **/
Pin[10, 20] = [GND, VCC];
/** Declarations and Intermediate Variables  **/

/** Logic Equations **/

/** Rs Latch **/
qst = !s
    # r & qst;

qsc = !r
    # s & qsc;

/** T flip - flop **/
qtt.d = pr
      # !clr & !t & qtt
      # !clr &  t & qtc;

qtc.d = clr
      # !pr & !t & qtc
      # !pr &  t & qtt;

/** D flip - flop **/
qdt.d = pr
      # d & !clr;

qdc.d = clr
      # !d & !pr;

/** JK flip - flop **/
qjt.d = pr
      # j & qjc & !clr
      # !k & qjt & !clr;

qjc.d = clr
      # !j & qjc & !pr
      #  k & qjt & !pr;

移位计数器设计--Protel99SE自带CUPL语言设计

Name        PLDDesign6            ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 11] = [clk, oe];
Pin[2] = [!clr];
/** Outputs **/
Pin[12..15] = [q3..0];

/** State Definitions **/
fld count = [q3..0];
fld clear = [!clr];

$define number0 'H'0
$define number1 'H'1
$define number2 'H'2
$define number3 'H'3
$define number4 'H'4
$define number5 'H'5
$define number6 'H'6
$define number7 'H'7
$define number8 'H'8
$define number9 'H'9
$define numbera 'H'a
$define numberb 'H'b
$define numberc 'H'c
$define numberd 'H'd
$define numbere 'H'e
$define numberf 'H'f

sequence count{

present number0:
        if clear next number0;
        default next number1;

present number1:
        if clear next number0;
        default next number2;

present number2:
        if clear next number0;
        default next number3;

present number3:
        if clear next number0;
        default next number4;

present number4:
        if clear next number0;
        default next number5;

present number5:
        if clear next number0;
        default next number6;

present number6:
        if clear next number0;
        default next number7;

present number7:
        if clear next number0;
        default next number8;

present number8:
        if clear next number0;
        default next number9;

present number9:
        if clear next number0;
        default next numbera;

present numbera:
        if clear next number0;
        default next numberb;

present numberb:
        if clear next number0;
        default next numberc;

present numberc:
        if clear next number0;
        default next numberd;

present numberd:
        if clear next number0;
        default next numbere;

present numbere:
        if clear next number0;
        default next numberf;

present numberf:
        next number0;

}

电梯数码管设计--Protel99SE自带CUPL语言设计

Name        PLDDesign4            ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 2, 3] = [l1call, l2call, l3call];
Pin[4, 5] = [f1_dira, f1_dirb];

/** Outputs **/
Pin[12, 14] = [uparrow, dnarrow];
Pin[15, 16] = [seg13, seg123];
Pin[17, 18] = [seg2, seg23];

/** Intermediate nodes  **/
up = !f1_dira;
dn =  f1_dira;
1floor = !f1_dira & !f1_dirb;
2floor = !1floor  & !3floor;
3floor =  f1_dira &  f1_dirb;

uparrow= up & (l2call # l3call);
dnarrow= dn & (l1call # l2call);

/** Table Inputs   Table Outputs **/
table 1floor,2floor,3floor => seg13, seg123, seg2, seg23 {
      'b'100 => 'b'1100;
      'b'010 => 'b'0111;
      'b'001 => 'b'1101;
}

差分控制器设计--Protel99SE自带CUPL语言设计

Name        PLDDesign9           ;
Partno                           ;
Revision    1                    ;
Date        3/12/02              ;
Designer    HotPower             ;
Company     Protel International ;
Assembly                         ;
Location                         ;
Device      g16v8                ;
Format      j                    ;

/*********************************************************************/
/* This PLD design (Revision 1) created on 3/12/02                   */
/*      for                   Protel International                   */
/*      and is stored as      PLDDesign                              */
/*********************************************************************/

/** Inputs  **/
Pin[1, 11]  = [clk, oe];
Pin[10,20]  = [Gnd,Vcc];
Pin[2..9]   =  [srclk2h, srclk2l, clrh, clrl, rclkh, rclkl, srclk1h, srclk1l];
/** Outputs **/
Pin[12..19] = [g, srclk2, q3..0, srclk1, rclk];

/** Declarations and Intermediate Variables  **/
fld count   = [q3..0];
fld clrx    = [clrh, clrl];
fld rclkx   = [rclkh, rclkl];
fld srclk1x = [srclk1h, srclk1l];
fld srclk2x = [srclk2h, srclk2l];

fld clrxx   = [g, srclk1h, srclk1l, srclk2h, srclk2l, clrh, clrl];
fld enxx    = [clrh, clrl, rclkh, rclkl];
fld rclkxx  = [g, rclkh, rclkl, srclk1h, srclk1l, srclk2h, srclk2l];
fld srclkxx = [g, clrh, clrl, rclkh, rclkl, srclk1h, srclk1l, srclk2h, srclk2l];

$define clear 'b'0101001

$define row0 'H'0
$define row1 'H'1
$define row2 'H'2
$define row3 'H'3
$define row4 'H'4
$define row5 'H'5
$define row6 'H'6
$define row7 'H'7
$define row8 'H'8
$define row9 'H'9
$define rowa 'H'a
$define rowb 'H'b
$define rowc 'H'c
$define rowd 'H'd
$define rowe 'H'e
$define rowf 'H'f

/** Logic Equations **/
    !g      = enxx: 'b'0101
            # enxx: 'b'0110
            # enxx: 'b'1001
            # enxx: 'b'1010;

    !rclk   = rclkxx: 'b'0011010;

    !srclk1 = srclkxx: 'b'010100110
            # srclkxx: 'b'010100101;

    !srclk2 = srclkxx: 'b'010101001
            # srclkxx: 'b'010100101;

/** State Definitions **/

sequence count{

present row0:
        if clrxx: clear next row0;
        default next row1;

present row1:
        if clrxx: clear next row0;
        default next row2;

present row2:
        if clrxx: clear next row0;
        default next row3;

present row3:
        if clrxx: clear next row0;
        default next row4;

present row4:
        if clrxx: clear next row0;
        default next row5;

present row5:
        if clrxx: clear next row0;
        default next row6;

present row6:
        if clrxx: clear next row0;
        default next row7;

present row7:
        if clrxx: clear next row0;
        default next row8;

present row8:
        if clrxx: clear next row0;
        default next row9;

present row9:
        if clrxx: clear next row0;
        default next rowa;

present rowa:
        if clrxx: clear next row0;
        default next rowb;

present rowb:
        if clrxx: clear next row0;
        default next rowc;

present rowc:
        if clrxx: clear next row0;
        default next rowd;

present rowd:
        if clrxx: clear next row0;
        default next rowe;

present rowe:
        if clrxx: clear next row0;
        default next rowf;

present rowf:
        next row0;

}