// *********************************************************************
// 数字钟VerilogHDL代码
//2007.7.27 by Levension @SCUT

//参考网上范例修改的
// *********************************************************************

module clock_main(clk_4Hz,mode,sel,add,alert,hour,min,sec,msec,LD);

input clk_4Hz;
input mode,sel,add;
output alert;
output [7:0] hour,min,sec,msec;
output [2:0] LD;

reg[7:0] hour,min,sec,msec,thour,tmin,tsec,ahour,amin,asec;
reg ath,atm,ats,aah,aam,aas;

reg [2:0]LD;

reg clk_1Hz,start,m_clk,h_clk;
reg [1:0] cnt,Nmode,Bsel;

wire ct1,ct2,ct3,cta,ctb,ctc;

parameter TIMER="2"'b00,
    SETTM="2"'b01,
    ALERT="2"'b10;

always @(posedge clk_4Hz)   //产生1Hz
   begin
   cnt<=cnt==3?0:cnt+1;
   if(cnt<2) clk_1Hz=0;
     else    clk_1Hz=1;
   end

always @(negedge mode)      //模式选择
  begin
  if(Nmode==2'd2) Nmode<=2'd0;
  else Nmode<=Nmode+1;
  end

always
  case(Nmode)                //发光二极管指示模式
   TIMER:LD<=3'b110;
    SETTM:LD<=3'b101;
    ALERT:LD<=3'b011;
  endcase

always @(negedge sel)         //调整位置选择 
  if(Nmode==SETTM||Nmode==ALERT)
       begin
       if(Bsel==2'd2) Bsel<=2'd0;
       else Bsel<=Bsel+1;
       end

always                       //add调整信号
begin
 case(Nmode)
 SETTM:                       //设置时间
  begin
   case(Bsel)
    2'd0:ath <=~add;
    2'd1:atm <=~add;
    2'd2:ats <=~add;
    endcase
   {aah,aam,aas}<=0;
  end
 ALERT:                         //设置闹鳞
  begin
  case(Bsel)
   2'd0:aah <=~add;
   2'd1:aam <=~add;
   2'd2:aas <=~add;
  endcase
  {ath,atm,ats} <=0;
  end
 default:
  {aah,aam,aas,ath,atm,ats}<=0;
 endcase
end

assign ct1=(ats&clk_4Hz)|(!ats&clk_1Hz); //ct1 用于计时、校时中的秒计数
assign ct2=(atm&clk_4Hz)|(!atm&m_clk);  //ct2 用于计时、校时中的分计数
assign ct3=(ath&clk_4Hz)|(!ath&h_clk);  //ct3用于计时、校时中的时计数

assign cta=(aas&clk_4Hz);              //cta用于闹铃秒计数
assign ctb=(aam&clk_4Hz);              //ctb用于闹铃分计数
assign ctc=(aah&clk_4Hz);             //ctc用于闹铃时计数

always @(posedge ct1)                  //秒计时和秒调整进程
begin
 if(tsec==8'h59)
    begin
    tsec<=0;
    m_clk<=1;
    end
 else
 begin
 if(tsec[3:0]==4'b1001)
   begin
   tsec[3:0]<=4'b0000;
   tsec[7:4]<=tsec[7:4]+1;
   end
 else tsec[3:0]<=tsec[3:0]+1;
    m_clk<=0;
 end
end

always @(posedge ct2) //分计时和分调整进程
begin
 if(tmin==8'h59)
  begin
  tmin <=0;
  h_clk <=1;
  end
  else
  begin
  if(tmin[3:0]==9)
  begin
  tmin[3:0]<=0;
  tmin[7:4]<=tmin[7:4]+1;
  end
  else tmin[3:0]<=tmin[3:0]+1;
  h_clk<=0;
  end
end

always @(posedge ct3)   //小时计时和小时调整进程
if(thour==8'h23) thour<=0;
else if(thour[3:0]==9)
begin
thour[7:4]<=thour[7:4]+1;
thour[3:0]<=0;
end
else thour[3:0]<=thour[3:0]+1;

always @(posedge cta)       //闹铃秒调整进程
begin
 if(asec==8'h59)
    asec<=0;
 else
 begin
 if(asec[3:0]==4'b1001)
   begin
   asec[3:0]<=4'b0000;
   asec[7:4]<=asec[7:4]+1;
   end
  else asec[3:0]<=asec[3:0]+1;
 end
end

always @(posedge ctb)        //闹铃分调整进程
begin
 if(amin==8'h59)
  amin <=0;
  else
  begin
  if(amin[3:0]==9)
  begin
  amin[3:0]<=0;
  amin[7:4]<=amin[7:4]+1;
  end
  else amin[3:0]<=amin[3:0]+1;
  end
end

always @(posedge ctc)                    //闹铃时调整进程
if(ahour==8'h23) ahour<=0;
else if(ahour[3:0]==9)
begin
ahour[7:4]<=ahour[7:4]+1;
ahour[3:0]<=0;
end
else ahour[3:0]<=ahour[3:0]+1;

assign alert=((ahour==thour)&&(amin==tmin)&&(Nmode==TIMER))?1:0;   //闹铃功能

always   //显示控制
case(Nmode)
TIMER: begin hour<=thour; min<=tmin; sec<=tsec; msec<=0; end
SETTM: begin hour<=thour; min<=tmin; sec<=tsec; msec<=0; end
ALERT: begin hour<=ahour; min<=amin; sec<=asec; msec<=0; end
endcase

endmodule

//************************************************************
//LED动态扫描verilog 代码，D1~8为数码管输入
//2007.07.26 By levension @SCUT
//************************************************************
module LED(clk,segout,bitout,D1,D2,D3,D4,D5,D6,D7,D8);

input clk;
input [3:0] D1,D2,D3,D4,D5,D6,D7,D8;
output [3:0] segout;
output [7:0] bitout;

reg [3:0] segout;
reg [7:0] bitout;

parameter S0=3'd0,            //采用状态机的方法
          S1=3'd1,
    S2=3'd2,
    S3=3'd3,
    S4=3'd4,
    S5=3'd5,
    S6=3'd6,
    S7=3'd7;

reg [2:0] state;
 
always @(posedge clk)
 begin
 case(state)
    S0:                                    //第1个数码管
  begin
  segout <=D1;
  bitout <=8'b0000_0001;
  state=S1;
  end
    S1:                                  //第2个数码管
  begin
  segout <=D2;
  bitout <=8'b0000_0010;
  state=S2;
  end
    S2:                                  //第3个数码管
  begin
  segout <=D3;
  bitout <=8'b0000_0100;
  state=S3;
  end
    S3:                                  //第4个数码管
  begin
  segout <=D4;
  bitout <=8'b0000_1000;
  state=S4;
  end
    S4:                                  //第5个数码管
  begin
  segout <=D5;
  bitout <=8'b0001_0000;
  state=S5;
  end
    S5:                                   //第6个数码管
  begin
  segout <=D6;
  bitout <=8'b0010_0000;
  state=S6;
  end
    S6:                                     //第7个数码管
  begin
  segout <=D7;
  bitout <=8'b0100_0000;
  state=S7;
  end
    S7:                                    //第8个数码管
  begin
  segout <=D8;
  bitout <=8'b1000_0000;
  state=S0;
  end
 endcase
 end
endmodule

今天，第一次在CPLD板上实现了第一个数字电路4×4键盘扫描的verilog 代码，欢迎大家讨论。

// *********************************************************************
// 键盘扫描VerilogHDL代码
//2007.7.26 by Levension @SCUT
// *********************************************************************

module keypad(keyval,y,x,clk);
   
    output [4:0] keyval; //返回的键值
    output [3:0] x;     //输出，列坐标
    input  [3:0] y;     //输入，行坐标
    input  clk;         //时钟源
   
    reg [4:0] keyval;
    reg [3:0] x;
   
    parameter clkdiv="2048"; 
    parameter S0=4'd0,      //状态机
              S1=4'd1,
              S2=4'd2,
              Wait="4"'d3,
              R0=4'd8,
              R0Temp=4'd9,
              R1=4'd10,
              R1Temp=4'd11,
              R2=4'd12,
              R2Temp=4'd13,
              R3=4'd14,
              R3Temp=4'd15;
             
    reg [3:0] state;
   
    reg [11:0] cnt;                        //2.048MHz，分频因子，分为1000Hz
    always @(posedge clk)
      cnt <= cnt==clkdiv ? 0 : cnt+1;
   
    reg clken;
    always @(posedge clk)
      clken <= cnt==clkdiv;
   
     always @(posedge clk)                 //键盘扫描部分
     if(clken)
       begin
       case(state)
           S0:              //判断是否按键按下
             begin
             x<=4'b0000;
             state="S1";
             end
            S1:
             begin
             if(y==4'b1111)  //无按键，返回
             state="S0";
             else
             x<=4'b0000;
             repeat(204800) @(posedge clk);  //延时100ms,消抖    
             state="S2";            
             end
            S2:
             begin
             if(y==4'b1111)
             state="S0";
             else
             state="R0Temp";                    
             end
            R0Temp:                              //扫描第一列
             begin
             x<=4'b1110;
             state="R0";
             end
            R0:
              case(y)
                  4'b1111:
                     state="R1Temp";
                  4'b0111:
                     begin
                     keyval<=5'd1;
                     state="Wait";
                     end
                  4'b1011:
                     begin
                     keyval<=5'd5;
                     state="Wait";
                     end
                  4'b1101:
                     begin
                     keyval<=5'd9;
                     state="Wait";
                     end
                  4'b1110:
                     begin
                     keyval<=5'd13;
                     state="Wait";
                     end
                   default:
                      state="Wait";  
                   endcase
               R1Temp:                              //扫描第二列
                begin
                x<=4'b1101;
                state="R1";
                end
               R1:
                 case(y)
                  4'b1111:
                     state="R2Temp";
                  4'b0111:
                     begin
                     keyval<=5'd2;
                     state="Wait";
                     end
                  4'b1011:
                     begin
                     keyval<=5'd6;
                     state="Wait";
                     end
                  4'b1101:
                     begin
                     keyval<=5'd10;
                     state="Wait";
                     end
                  4'b1110:
                     begin
                     keyval<=5'd14;
                     state="Wait";
                     end
                   default:
                      state="Wait";  
                    endcase
              R2Temp:                                   //扫描第三列
               begin
               x<=4'b1011;
               state="R2";
               end
               R2:
               case(y)
                  4'b1111:
                     state="R3Temp";
                  4'b0111:
                     begin
                     keyval<=5'd3;
                     state="Wait";
                     end
                  4'b1011:
                     begin
                     keyval<=5'd7;
                     state="Wait";
                     end
                  4'b1101:
                     begin
                     keyval<=5'd11;
                     state="Wait";
                     end
                  4'b1110:
                     begin
                     keyval<=5'd15;
                     state="Wait";
                     end
                   default:
                     state="Wait";  
                   endcase
             R3Temp:                                //扫描第四列
               begin
               x<=4'b0111;
               state="R3";
               end
             R3:
               case(y)
                  4'b1111:
                     state="Wait";
                  4'b0111:
                     begin
                     keyval<=5'd4;
                     state="Wait";
                     end
                  4'b1011:
                     begin
                     keyval<=5'd8;
                     state="Wait";
                     end
                  4'b1101:
                     begin
                     keyval<=5'd12;
                     state="Wait";
                     end
                  4'b1110:
                     begin
                     keyval<=5'd16;
                     state="Wait";
                     end
                   default:
                      state="Wait";
                   endcase
                Wait:                                      //返回S0状态
                   state="S0"; 
                endcase
           end
       
endmodule