同学问我一道O2的笔试题，

module   C_case1(clk,out1);
input  clk;
output out1;

reg  state1;
reg  out1;

always @(posedge clk)
  case(state1)
   0: state1<=1;
 1: state1<=0;
  endcase
always @(state1)
  case(state1)
   0: out1<=1;
 1: out1<=0;
 endcase
endmodule

 module   C_case2(clk,out2);
input  clk;
output out2;

reg  state2;
reg  out2;
 
 always @(posedge clk)

  case(state2)
   0:begin
 state2<=1;
   out2<=1;
   end
 1:begin
 state2<=0;
   out2<=0;
   end
   endcase
 
 
 endmodule

两者资源比较。

在Quartus综合结果如下：

第一种：

组合Case

第二种：

时序Case

明显第一种比第二种省个触发器

工程文件打包如下：

一、

//Simple module that connect sthe SW switches to the LEDR lights
module part1(SW,LEDR);
  input [17:0] SW;//toggleswitches
output[17:0]LEDR;//redLEDs
assignLEDR=SW;
endmodule

二、

// Implements eight 2-to-1 multiplexers.
// inputs:  SW7-0 represent the 8-bit input X, and SW15-8 represent Y
//            SW17 selects either X or Y to drive the output LEDs
// outputs:  LEDR17-0 show the states of the switches
//               LEDG7-0 shows the outputs of the multiplexers
module part2 (SW, LEDR, LEDG);
   input [17:0] SW;         // toggle switches
   output [17:0] LEDR;   // red LEDs
   output [7:0] LEDG;    // green LEDs

   wire Sel;
   wire [7:0] X, Y, M;

   assign  LEDR = SW;
   assign  X        = SW[7:0];
   assign  Y        = SW[15:8];
   assign  Sel      = SW[17];

   assign M[0] = (~Sel & X[0]) | (Sel & Y[0]);
   assign M[1] = (~Sel & X[1]) | (Sel & Y[1]);
   assign M[2] = (~Sel & X[2]) | (Sel & Y[2]);
   assign M[3] = (~Sel & X[3]) | (Sel & Y[3]);
   assign M[4] = (~Sel & X[4]) | (Sel & Y[4]);
   assign M[5] = (~Sel & X[5]) | (Sel & Y[5]);
   assign M[6] = (~Sel & X[6]) | (Sel & Y[6]);
   assign M[7] = (~Sel & X[7]) | (Sel & Y[7]);
   assign LEDG[7:0] = M;
endmodule

三、

// Implements a 3-bit wide 5-to-1 multiplexer.
// inputs: SW14-0 represent data in 5 groups, U-Y
//           SW17-15 selects one group from U to Y
// outputs: LEDR17-0 show the states of the switches
//             LEDG2-0 displays the selected group
module part3 (SW, LEDR, LEDG);
   input [17:0] SW;    // toggle switches
   output [17:0] LEDR;   // red LEDs
   output [2:0] LEDG;   // green LEDs

   wire [1:3] m_0, m_1, m_2; // m_0 is used for 3 intermediate multiplexers 
                                             // to produce the 5-to-1 multiplexer M[0], m_1 is for
                                            // M[1], and m_2 is for M[2]
   wire [2:0] S, U, V, W, X, Y, M; // M is the 3-bit 5-to-1 multiplexer

   assign S[2:0] = SW[17:15];
   assign U = SW[2:0];
   assign V = SW[5:3];
   assign W = SW[8:6];
   assign X = SW[11:9];
   assign Y = SW[14:12];

   assign LEDR = SW;

   // 5-to-1 multiplexer for bit 0
   assign m_0[1] = (~S[0] & U[0]) | (S[0] & V[0]);
   assign m_0[2] = (~S[0] & W[0]) | (S[0] & X[0]);
   assign m_0[3] = (~S[1] & m_0[1]) | (S[1] & m_0[2]);
   assign M[0] = (~S[2] & m_0[3]) | (S[2] & Y[0]); // 5-to-1 multiplexer output

   // 5-to-1 multiplexer for bit 1
   assign m_1[1] = (~S[0] & U[1]) | (S[0] & V[1]);
   assign m_1[2] = (~S[0] & W[1]) | (S[0] & X[1]);
   assign m_1[3] = (~S[1] & m_1[1]) | (S[1] & m_1[2]);
   assign M[1] = (~S[2] & m_1[3]) | (S[2] & Y[1]); // 5-to-1 multiplexer output
 
  // 5-to-1 multiplexer for bit 2
   assign m_2[1] = (~S[0] & U[2]) | (S[0] & V[2]);
   assign m_2[2] = (~S[0] & W[2]) | (S[0] & X[2]);
   assign m_2[3] = (~S[1] & m_2[1]) | (S[1] & m_2[2]);
   assign M[2] = (~S[2] & m_2[3]) | (S[2] & Y[2]); // 5-to-1 multiplexer output
 
   assign LEDG[2:0] = M;
endmodule

四、

// Implements a circuit that can display five characters on a 7-segment
// display.
// inputs: SW2-0 selects the letter to display. The characters are:
//  SW 2 1 0  Char
//  ----------------
//     0 0 0   'H'
//   0 0 1  'E'
//   0 1 0  'L'
//   0 1 1  'O'
//   1 0 0  ' ' Blank
//   1 0 1  ' ' Blank
//   1 1 0  ' ' Blank
//   1 1 1  ' ' Blank
//
// outputs: LEDR2-0 show the states of the switches
//    HEX0 displays the selected character
module part4 (SW, LEDR, HEX0);
   input [2:0] SW;    // toggle switches
   output [2:0] LEDR;   // red LEDs
   output [0:6] HEX0;   // 7-seg display

   wire [2:0] C;

   assign LEDR = SW;
   assign C[2:0] = SW[2:0];

 /*
  *       0 
  *      --- 
  *     |   |
  *    5|   |1
  *     | 6 |
  *      --- 
  *     |   |
  *    4|   |2
  *     |   |
  *      --- 
  *       3 
  */
 // the following equations describe HEX0[0-6] in cannonical SOP form
   assign HEX0[0] = ~((~C[2] & ~C[1] & C[0]) | (~C[2] & C[1] & C[0]));
   assign HEX0[1] = ~((~C[2] & ~C[1] & ~C[0]) | (~C[2] & C[1] & C[0]));
   assign HEX0[2] = ~((~C[2] & ~C[1] & ~C[0]) | (~C[2] & C[1] & C[0]));
   assign HEX0[3] = ~((~C[2] & ~C[1] & C[0]) | (~C[2] & C[1] & ~C[0]) |
                               (~C[2] & C[1] & C[0]));
   assign HEX0[4] = ~((~C[2] & ~C[1] & ~C[0]) | (~C[2] & ~C[1] & C[0]) |
                               (~C[2] & C[1] & ~C[0]) | (~C[2] & C[1] & C[0]));
   assign HEX0[5] = ~((~C[2] & ~C[1] & ~C[0]) | (~C[2] & ~C[1] & C[0]) |
                               (~C[2] & C[1] & ~C[0]) | (~C[2] & C[1] & C[0]));
   assign HEX0[6] = ~((~C[2] & ~C[1] & ~C[0]) | (~C[2] & ~C[1] & C[0]));
endmodule