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VGA接口之硬件结构

英文版见: http://blog.ednchina.com/likee/111647/message.aspx

        一个VGA显示器接口显示一个图片需要五个信号:

        一、R、G和B信号,也就是红、绿、蓝三原色。

        二、HS和VS(水平同步信号和垂直同步信号)。

R、G、B三原色是模拟信号,HS和VS是数字信号。

下面介绍如何驱动VGA连接器:

VGA接口的脚13和14(HS和VS)是数字信号,所以可以直接通过FPGA的两个IO口来控制(或者还可以接上低阻值的电阻,比如:10欧或者20欧)。

脚1、2和3(R、 G 和 B)是常值为0.7V的75欧的模拟信号。由3.3V的FPGA管脚输出,用三个270欧的电阻刚好满足要求。连接头输入的电压驱动电阻为75欧,所以3.3V变成为:3.3*75/(270+75)=0.72V , 非常接近0.7V。用不同的0和1的组合驱动三条线,不难算出可以达到8种颜色。

5, 6, 7, 8 和 10脚接地。

VGA的扫描方式是非交叉式扫描。

同步的极性: 水平和垂直方向都是低电平有效。

 

 

 

系统分类: 模拟技术
用户分类: 接口技术
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国外VHDL& Verilog IP Resource 下载网站列表
http://www.opencores.org/ Open Cores Repository.
The Open Cores web site seems to be the central repository for a wide variety of computer peripheral designs and is definitely worth checking out. The Open Cores site has a link page to other resources, so I won't include them all here.
http://www.fpgacpu.org Jan Gray's Risc CPU Web Site
Jan Gray has a XR16 RISC CPU , GR000 RISC CPU and XSOC (System on a Chip). He also runs the FPGA CPU mailing list.
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ John Williams MicroBlaze uCLinux Web Site.
John Williams is a Professor at the School of Information Technology and Electrical Engineering at the University of Queensland. He runs quite an active mailing list for implementing uCLinux on the Xilinx MicroBlaze soft-core processor.
http://www.birdcomputer.ca/ Robert Finch's Bird Computer - FPGA Cores
Robert has a variety of CPU, video, audio, timekeeping and keyboard projects for download on his web site.
http://www.fpga4fun.com/
Various FPGA projects for the hobbyist. Includes information for connecting devices such as LCD Displays and R/C Servos to FPGAs.
http://www.retromicro.com Doug Hodson's Web Page
Doug has implemented a few projects using the XESS XSA100 FPGA Board. Doug's project page has some examples of VGA video generators. The XSA is quite a nice little board with Flash memory and Dynamic RAM, although the XSA100 uses a smaller FPGA and access to static RAM conflicts with some of the I/O pins. The XSA100 uses a XC2S100 FPGA and can be purchased with the XStend prototyping motherboard. For more details check out  http://www.xess.com . They have all the manuals on their web site. The XESS documentation is quite good.
http://www.fpgaarcade.com
MikeJ's complete PACMAN, Space Invaders, and Galaxians in FPGA !
http://members.iinet.net.au/~msmcdoug/ Mark's Perpetually WIP Home page
Mark's Vic20, ZX81 and Arcade game web page. (Also includes some work on the CoCo).
http://www.geocities.com/gary_l_becker/ Gary's OSI-APPLE-SOC
OSI-SOC is a project to build an enhanced Ohio Scientific Inc Superboard / C1P System On a Chip using a Xilinx FPGA (XC3S1000 Spartan 3 Starter Board). OSI-APPLE-SOC adds an Apple ][e on the same FPGA.
http://www.geocities.com/gary_L_becker/coco3fpga.html CoCo3 FPGA
Gary's CoCo3 on an FPGA.
http://www.madscientistroom.org/fpga/
Randy Thelen has a good User Constraint File generator amongst his FPGA bits and pieces.
http://www.cs.ucr.edu/~dalton/i8051/
The Dalton Project at the University of California Computer Science Dept in Riversdale have an  Intel 8051 core. There is a synopsis model as well as C++ simulator for the 8051.
http://www.dte.eis.uva.es/OpenProjects/OpenDSP/index.htm
The Department of Electronic Technology at the University of Valladolid in Spain have an Open DSP design which can be found on their web site.
[url=http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html]http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html[/url]
University of Hamburg VHDL Page. Assorted VHDL tools and microprocessor cores.
http://www.opencores.org/people.cgi/info/jesus
Daniel Wallner's  Soft Cores Web site is now on Open Cores with five synthesizable microprocessor cores: PPX16 (PIC16C55, PIC16F84), T80 (Z80), T51 (8051), T65 (6502) and AX8 (90S1200, 90S2313).
http://indi.hpsdr.com/
K Ring Technologies Semiconductor Indi16 16n bit Forth CPU. Designed for Altera Quartus II software.
http://www.gmvhdl.com/downloads.html
Green Mountains Computing Systems have a  MC68HC11 VHDL core as well as VHDL tools and simulators. I tried compiling this core under the Xilinx ISE 4.1 Webpack software and it used 200% of the XC2S200 resource, so it is not an efficient design. Later versions of Xilinx ISE Webpack may be more efficient.
http://www.mcmanis.com/chuck/robotics/fpga/index.html
Chuck McManis has put up a web site with a list of his projects for the B3-SPARTAN2+ board.
http://zxgate.sourceforge.net/
For some fun, projects on the net, using Z80 cpus implemented completely in the FPGA. Daniel Wallner's computers using FPGA T80 cores .
http://server.opensourcedepot.com/
Pat's Open Source Depot. Although there are no FPGA projects listed, Pat used to run a small mailing list for Hobby Computer designers. The mailing list included a small group of people interested in designing with the 6809 and the Burch ED Spartan FPGA boards.
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The hardware of the VGA interface :

中文版见: http://blog.ednchina.com/likee/111649/message.aspx

 

A VGA monitor requires 5 signals to display a picture:

R, G and B (red, green and blue signals).

HS and VS (horizontal and vertical synchronization).

 

 

The R, G and B are analog signals, while HS and VS are digital signals.

Here's how to drive the VGA connector:

Pins 13 and 14 of the VGA connector (HS and VS) are digital signals, so can be driven directly from two FPGA pins (or through low values resistors, like 10Ω or 20Ω).

Pins 1, 2 and 3 (R, G and B) are 75Ω analog signals with nominal values of 0.7V. With 3.3V FPGA outputs, use three 270Ω series resistors. The resistors form voltage dividers with the 75Ω resistors in the monitor inputs so that 3.3V become 3.3*75/(270+75)=0.72V, pretty close to 0.7V. Driving these 3 pins with different combinations of 0's and 1's gives us up to 8 colors.

Ground pins are pins 5, 6, 7, 8 and 10.

Scan type: non interlaced.

Sync polarity: H negative, V negative.

 

 

 

 

系统分类: 模拟技术
用户分类: 接口技术
标签: VGA
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