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面阵 CCD LZ23BP2 驱动
module LZ23BP2(CLK,V1,V2,V3,V4,H1,H2,RS,OFD);
output V2,V4,H1,H2,RS,OFD;
output[1:0] V3,V1;
input CLK;
reg H1,V2,V4,RS,OFD;
reg[1:0] V1,V3;
reg HD,VD;
reg Fclk;
reg[1:0] Fclk2;
reg[9:0] q_Horizontal;
reg[9:0] q_Vertical;
assign H2 = ~H1; //H2
always@(posedge CLK) //H1
begin
if(!Fclk) H1 = ~H1;
Fclk = ~Fclk;
end
always@(posedge CLK) //RS
begin
if(!Fclk2) RS = 1;
else RS = 0;
Fclk2 = Fclk2+1;
end
always@(negedge H1)
begin
if(q_Horizontal >= 779) q_Horizontal = 0;
else q_Horizontal = q_Horizontal+1;
end
always@(posedge H1) //HD,V1,V2,V3,V4,OFD;
begin
if( (q_Horizontal>=0) && (q_Horizontal<77) ) HD <= 1; //HD
else HD <= 0;
if( (q_Horizontal>=58) && (q_Horizontal<86) ) V2 <= 0; //V2
else V2 <= 1;
if( (q_Horizontal>=51) && (q_Horizontal<93) ) V4 <= 1; //V4
else V4 <= 0;
if( (q_Horizontal>=65) && (q_Horizontal<82) ) OFD <= 1; //OFD
else OFD <= 0;
if(q_Vertical == 19)
begin
if( (q_Horizontal>=398) &&(q_Horizontal<460) ) V1 <= 2; //V1
else if( (q_Horizontal>=44) && (q_Horizontal<72) ) V1 <= 0;
else V1 <= 1;
if( (q_Horizontal>=37) && (q_Horizontal<79) || (q_Horizontal>=275) && (q_Horizontal<460) || (q_Horizontal>=522) ) V3 <= 1; //V3
else if( (q_Horizontal>=460) && (q_Horizontal<522) ) V3 <= 2;
else V3 <= 0;
end
else
begin
if( (q_Horizontal>=44) && (q_Horizontal<72) ) V1 <= 0; //V1
else V1 <= 1;
if( (q_Horizontal>=37) && (q_Horizontal<79) ) V3 <= 1; //V3
else V3 <= 0;
end
end
always@(negedge HD)
begin
if(q_Vertical >= 524) q_Vertical = 0;
else q_Vertical = q_Vertical + 1;
end
always@(posedge HD) //VD
begin
if( (q_Vertical>=0) && (q_Vertical<9) ) VD <= 1;
else VD <= 0;
end
endmodule
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