标签： VHDL  超声波测距  源代码  

VHDL超声波测距源代码

VHDL超声波测距源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_40KHz_1Hz is
port(clk,rsignal:in std_logic;--rsignal 回波信号
  sel:out std_logic_vector(3 downto 0);
  q:out std_logic_vector(7 downto 0);
  ssignal:out std_logic
  );--ssignal 发射信号
end ;

architecture nidiya of clk_40KHz_1Hz is
type state is(st0,st1,st2);
signal crst,en,clr,clk1,clk2,clk3,clk40hz:std_logic;
signal etime1,count1:integer range 0 to 10000;
signal asm:state;
begin

--分频部分(产生1MHZ的信号)
process(clk)
variable cnt:integer range 0 to 50;
begin
if clk'event and clk='1' then cnt:=cnt+1;
if cnt<25 then clk1<='0';
elsif cnt<50 then clk1<='1';
else cnt:=0;clk1<='0';
end if;
end if;
end process;

--40KHZ信号
process (clk)
variable a:integer range 0 to 1250 ;--1250
begin
if rising_edge(clk) then a:=a+1;
if a<625 then clk40hz<='0';
elsif a<1250 then clk40hz<='1';
else a:=0;clk40hz<='0';
end if ;
end if;
end process;

--1S延时
process(clk)
variable e:integer range 0 to 100000000;
begin
if rising_edge(clk) then e:=e+1;
if e<99990000 then clk2<='0';--49990000
elsif e<100000000 then clk2<='1';
else e:=0;clk2<='0';
end if;
end if;
end process;
ssignal<=(clk2 and clk40Hz);
--状态转换部分
process(clk1)
begin
if   clk1'event and clk1='1' then
case asm is
  when st0=>en<='0';
          clr<='0';
          if clk2='1' then asm<=st1;
          else
          asm<=st0;
          end if;
  when st1=>en<='1';
          clr<='0';
          if rsignal='1' then asm<=st2;
          end if;
    when st2=>en<='0';
          clr<='1';
        if rsignal='0' then   asm<=st0;
        elsif clk2='1' then asm<=st1;
        end if;
  when others=>en<='0';clr<='0';asm<=st0;
end case;  
end if;
end process;


--计数部分
process(clk1)
begin
if clr='1' then etime1<=count1;
elsif clk2='1' then count1<=0;
elsif en='1' then
if clk1'event and clk1='1' then count1<=count1+1;
end if;
end if;
end process;



process(clk)
variable cnt:integer range 0 to 250000;
begin
if clk'event and clk='1' then cnt:=cnt+1;
if cnt<125000 then clk3<='0';
elsif cnt<250000 then clk3<='1';
else cnt:=0;clk3<='0';
end if;
end if;
end process;

--显示部分译码
process(clk3)
variable seg_sel:integer range 0 to 3;
variable x1:integer range 0 to 9;
variable xx:integer range 0 to 10000;
begin
if clk3'event and clk3='1' then seg_sel:=seg_sel+1;
if seg_sel>3 then seg_sel:=0;
end if;
case seg_sel is
when 0 =>sel<="1000";
when 1 =>sel<="0100";
when 2 =>sel<="0010";
when 3 =>sel<="0001";
when others=>sel<="0000";
end case;
if seg_sel=3 then
x1:=etime1/1000;
xx:=etime1-x1*1000;
elsif seg_sel=2 then
x1:=xx/100;
xx:=xx-x1*100;
elsif seg_sel=1 then
x1:=xx/10;
xx:=xx-x1*10;
elsif seg_sel=0 then
x1:=xx;

end if;
case x1 is
when 0 =>q<="11000000";--0
when 1 =>q<="11111001";--1
when 2 =>q<="10100100";--2
when 3 =>q<="10110000";--3
when 4 =>q<="10011001";--4
when 5 =>q<="10010010";--5
when 6 =>q<="10000010";--6
when 7 =>q<="11111000";--7
when 8 =>q<="10000000";--8
when 9 =>q<="10010000";--9
when others=>q<="11111111";
end case;
end if;
end process;
end nidiya;

系统分类: CPLD/FPGA   |   用户分类: FPGA/VHDL   |   来源: 原创   |   【推荐给朋友】