自己动手制做一把“电蚊拍”。有了它，保管让家中的蚊子死个光，全家人安安稳稳睡好觉！
　　一、工作原理
　　电蚊拍的电路如图1所示，它主要由高频振荡电路、三倍压整流电路和高压电击网DW三部分组成。


　　当按下电源开关SB时，由三极管VT和变压器T构成的高频振荡器通电工作，把3V直流电变成18kHz左右的高频交流电，经T升压到约500V（L3两端实测），再经二极管VD2～VD4、电容器C1～C3三倍压整流升高到1500V左右，加到蚊拍的金属网DW上。当蚊蝇触及金属网丝时，虫体造成电网短路，即会被电流、电弧杀灼或击晕、击毙。
　　电路中，发光二极管VD1和限流电阻器R1构成指示灯电路，用来指示电路通断状态及显示电池电能的耗损情况。

　　二、元器件选择
　　晶体管VT选用2N5609型硅NPN中功率三极管，亦可用8050、9013型等常用三极管代替。VD1用φ3mm红色发光二极管，VD2～VD4用1N4007型硅整流二极管。
　　R1～R3均用RTX-1/8W型碳膜电阻器。C1～C3一律用CL11-630V型涤纶电容器，SB用6mm×6mm立式微型轻触开关。G用5号干电池两节串联（配塑料电池架）而成，电压3V。
　　高频变压器T须自制：选用2E19型铁氧体磁芯及配套塑料骨架，L1用φ0.22mm漆包线绕22匝，L2用同号线绕8匝，L3用φ0.08mm漆包线绕1400匝左右。注意图中黑点为同名端，头尾顺序绕，绕组间垫一、二层薄绝缘纸。

　　三、制作与使用
　　图2所示为该电蚊拍的印制电路板焊接图。印制电路板最好采用环氧基质单面铜箔板制作，实际尺寸约为56mm×28mm。


　　整个电蚊拍可用旧的非金属羽毛球拍作骨架组装。拆掉羽毛球拍上原有的网线和手柄，按图3所示用φ1mm左右镀锌铁丝在球拍上平行布线，间距不大于 4mm。两组网线可有意布在不同平面上，这样可避免因人手误碰网线而发生的电击现象，但对电击蚊蝇效果无影响。另用180mm×35mm×20mm塑料盒或φ35mm×180mm硬塑料管加工制成手柄，将电路板、电池架装入，并在合适位置处开孔固定按钮开关SB和发光二极管VD1。最后用热熔胶固定网拍，把网拍两电极引线焊在电路板上R3两端即成。只要焊装正确无误，无须任何调试便可投入使用。

　　使用时，手握网拍把柄，按下按钮开关，像使用普通蚊蝇拍一样挥拍，让网面触及飞动的蚊子（或苍蝇、飞蛾），即可迅速将其击毙。该电蚊拍耗电省，工作电流实测约120mA左右，每换一次新电池可使用数月。由于其输出功率有限（瞬间短路电流实测≤1.5mA），故对人及宠物绝对安全。当人体不慎触及网面时，仅会发生局部短暂麻刺。但注意不要在严禁烟火的场所或水中使用。当网面上粘有残余虫骸时，可用毛刷清除或直接抖落，勿用湿布或水擦洗，必要时可用棉花浸酒精清擦。

转贴自:http://www.51c51.net/article/2008/0331/article_3689.html

     This KIT is designed 30 years ago,it amuses a lot of people.

     I think in the original Quad405,LM301 is not a fast OP.
So,the C8 120pf capacitor  used here as the feedforward network.
the high frequency part of signal went stright into the current dumper(push/pull pair transisters).bypass the Tr3-Tr5,Tr7 transisters.

47ohm and L2 3uH，together with R5, as feedback（current parallel negative feedback ）.

so,the total gain is Io="A"*Ii,current dump to the speaker.

差分输入+共发射级放大+推挽射级跟随器

基本思路是从一个类OP的电路（铃木雅臣的书上的4549）变形，加大输出级的电流。

网上找来了ALU的VHDL代码：

alu 1.1 vhd

--
-- Project
--    pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
--    AVR core, but about 3x faster in terms of both clock frequency and MIPS.
--    The increase in speed comes from a relatively deep pipeline. The original
--    AVR core has only two pipeline stages (fetch and execute), while pAVR has
--    6 pipeline stages:
--       1. PM    (read Program Memory)
--       2. INSTR (load Instruction)
--       3. RFRD  (decode Instruction and read Register File)
--       4. OPS   (load Operands)
--       5. ALU   (execute ALU opcode or access Unified Memory)
--       6. RFWR  (write Register File)
-- Version
--    0.32
-- Date
--    2002 August 07
-- Author
--    Doru Cuturela, doruu@yahoo.com
-- License
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU General Public License as published by
--    the Free Software Foundation; either version 2 of the License, or
--    (at your option) any later version.
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU General Public License for more details.
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
--

--
-- This is pAVR's ALU.
-- The ALU asychronousely computes:
--    - output
--    - output flags,
--    based on:
--    - input 1
--    - input 2
--    - input flags
-- Flags:
--    - C (cary)
--    - Z (zero)
--    - N (negative)
--    - V (two's complement overflow)
--    - S (N xor V, for signed tests)
--    - H (half carry)
--       *** The half carry is computed as specified in the AVR instruction set.
--       However, Atmel's AVRStudio computes it differently. To see where is the
--       bug, in the AVR instruction set document or in AVRStudio.
--

--
library work;
use work.std_util.all;
use work.pavr_util.all;
use work.pavr_constants.all;
library ieee;
use ieee.std_logic_1164.all;

entity pavr_alu is
   port(
      pavr_alu_op1:      in  std_logic_vector(15 downto 0);
      pavr_alu_op2:      in  std_logic_vector(7 downto 0);
      pavr_alu_out:      out std_logic_vector(15 downto 0);
      pavr_alu_opcode:   in  std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
      pavr_alu_flagsin:  in  std_logic_vector(5 downto 0);
      pavr_alu_flagsout: out std_logic_vector(5 downto 0)
   );
end;

architecture pavr_alu_arch of pavr_alu is
   -- Wires
   signal tmp10_1, tmp10_2, tmp10_3 : std_logic_vector(9 downto 0);
   signal tmp18_1, tmp18_2, tmp18_3 : std_logic_vector(17 downto 0);

   signal pavr_alu_h_sel: std_logic_vector(pavr_alu_h_sel_w - 1 downto 0);
   signal pavr_alu_s_sel: std_logic;
   signal pavr_alu_v_sel: std_logic_vector(pavr_alu_v_sel_w - 1 downto 0);
   signal pavr_alu_n_sel: std_logic_vector(pavr_alu_n_sel_w - 1 downto 0);
   signal pavr_alu_z_sel: std_logic_vector(pavr_alu_z_sel_w - 1 downto 0);
   signal pavr_alu_c_sel: std_logic_vector(pavr_alu_c_sel_w - 1 downto 0);

   signal pavr_alu_out_int: std_logic_vector(15 downto 0);
   signal pavr_alu_flagsout_int: std_logic_vector(5 downto 0);

   -- Registers
   --    No registers
begin

   -- Compute ALU output and selectors for flags muxers.
   alu_out:
   process(pavr_alu_op1, pavr_alu_op2, pavr_alu_out_int, pavr_alu_opcode, pavr_alu_flagsin,
           tmp10_1, tmp10_2, tmp10_3,
           tmp18_1, tmp18_2, tmp18_3
          )
   begin
      -- Default ALU output to 0.
      pavr_alu_out_int <= int_to_std_logic_vector(0, pavr_alu_out_int'length);

      -- Default 8 bit adders's operands to ls8bits(operand1), operand2, carry in and carry out to 0.
      tmp10_1(0) <= '0';
      tmp10_2(0) <= '0';
      tmp10_1(8 downto 1) <= pavr_alu_op1(7 downto 0);
      tmp10_2(8 downto 1) <= pavr_alu_op2(7 downto 0);
      tmp10_1(9) <= '0';
      tmp10_2(9) <= '0';

      -- Default 16 bit adders's operands to operand1, signExtendTo16bits(operand2), carry in and carry out to 0.
      tmp18_1(0) <= '0';
      tmp18_2(0) <= '0';
      tmp18_1(16 downto 1) <= pavr_alu_op1(15 downto 0);
      tmp18_2(16 downto 1) <= sign_extend(pavr_alu_op2, 16);
      tmp18_1(17) <= '0';
      tmp18_2(17) <= '0';

      -- Default adders's outputs
      tmp10_3 <= int_to_std_logic_vector(0, tmp10_3'length);
      tmp18_3 <= int_to_std_logic_vector(0, tmp18_3'length);

      -- Default flags out to flags in.
      pavr_alu_h_sel <= pavr_alu_h_sel_same;
      pavr_alu_s_sel <= pavr_alu_s_sel_same;
      pavr_alu_v_sel <= pavr_alu_v_sel_same;
      pavr_alu_n_sel <= pavr_alu_n_sel_same;
      pavr_alu_z_sel <= pavr_alu_z_sel_same;
      pavr_alu_c_sel <= pavr_alu_c_sel_same;

      -- Build ALU output.
      case std_logic_vector_to_nat(pavr_alu_opcode) is
         when pavr_alu_opcode_add8 =>
            tmp10_3 <= tmp10_1 + tmp10_2;
            pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
            pavr_alu_h_sel <= pavr_alu_h_sel_add8;
            pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
            pavr_alu_v_sel <= pavr_alu_v_sel_add8;
            pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
            pavr_alu_z_sel <= pavr_alu_z_sel_z8;
            pavr_alu_c_sel <= pavr_alu_c_sel_add8;
         when pavr_alu_opcode_adc8 =>
            tmp10_1(0) <= pavr_alu_flagsin(0);
            tmp10_2(0) <= pavr_alu_flagsin(0);
            tmp10_3 <= tmp10_1 + tmp10_2;
            pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
            pavr_alu_h_sel <= pavr_alu_h_sel_a