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S3C2410A is a 16/32 bit RISC microprocessor . This product is designed to provide hand-held device and general applications with cost-effective , low power and high-performance micro-controller solution in small die size .
S3C2410A was developed using an ARM920T core , 0.18um CMOS standard cells and a memory complier . Its low power , simple , elegant and fully static design is partically suitable for cost and power-sensitive applications . It adopts a new bus architeture called advanced microcontroller bus architeture (AMBA) .
S3C2410A offers outstanding features with its cpu core . A 16/32 bit ARM920T RISC processor designed by Advanced RISC Machines , Ltd. The ARM920T implements MMU , AMBA BUS ,and Harvard cache architeture with separated 16k instruction and 16k data caches , each with a 8-word line length .
By providing a complete set of common system peripherals , the S3C2410A minimizes overall system costs and eliminates the need to configure additional components . The integrated on-chip functions that are descriped in this document include.
1. 1.8V/2.0V int. , 3.3V memory , 3.3V external I/O microprocessor with 16KB I-cache/16KB D-cache/MMU
2. External memory controller (SDRAM controller and Chip Select logic)
3. LCD controller wiht 1-ch LCD-dedicated DMA
4. 4-ch DMA with external request pins
5. 3-ch UART / 2-ch SPI
6. 1-ch multi-master IIC-BUS / 1-ch IIS-BUS controller
7. SD host interface version 1.0 & Multi-media Card Protocol version 2.11 compatible
8. 2-port USB host / 1-port USB device
9. 4-ch PWM timers / 1-ch internal timer
10. 117-bit general purpose I/O ports /24-ch external interrupt source
11. Power controll: Normal , Slow , Idle & Power off mode
12. 8-ch 10 bit ADC & Touch Screen Interface .
13. RTC With calendar function
14. On-chip clock generator with PLL
A. Bus Controller
OM[1:0] sets S3C2410 in the test mode , which is used only at fabrication . Also, it determines the bus width of nGCS0 . The pull up/down resister determines the logic level during the RESET cycle . 00: nand-boot 01: 16-bit 10: 32-bit 11: Test Mode
ADDR[26:0] Outputs the memory address of the corresponding bank .
DATA[31:0] Input data during memory read and output data during memory write . The bus width is programmable among 8/16/32 bits .
nGCS[7:0] activated when the address of a memory is within the address region of each bank . The number of access cycles and the bank size can be programmed .
nWE indicate that the current bus cycle is a write cycle .
nOE indicate that the current bus cycle is a read cycle .
nXBREQ allows another bus master to request of the local bus . Back active indicates that bus control has been granted .
nXBACK indicates that the S3C2410A has surrendered control of the local bus to another bus master .
nWAIT nWAIT requests to prolong a current bus cycle . As long as nWAIT is L , the current bus cycle cann`t be completed . If nWAIT signal isn`t used in your system , nWAIT signal must be tied on pull-up resistor .
B. SDRAM/SRAM
nSRAS SDRAM Row Address Strobe .
nSCAS SDRAM Column Address Strobe .
nSCS[1:0] SDRAM chip select
DQM[3:0] SDRAM data mask
SCLK[1:0] SDRAM clock
SCKE SDRAM clock enable
nBE[3:0] upper byte/lower byte enable (in case of 16-bit SRAM)
nWE[3:0] write byte enable
C. NAND FLASH
CLE command latch enable
ALE address latch enable
nFCE Nand Flash Chip Enable
nFRE Nand Flash Read Enable
nFWE Nand Flash Write Enable
NCON Nand Flash Configuration , if nand flash controller isn`t used , it has to be tied on pull-up resistor .
R/nB Nand Flash Ready/Busy , if nand flash controller isn`t used , it has to be tied on pull-up resistor .
D. LCD Control Unit
VD[23:0] STN/TFT/SEC TFT: LCD data bus ...
LCD_PWREN STN/TFT/SEC TFT : LCD panel power enable control signal ...
VCLK STN/TFT : LCD clock signal ...
VFRAME STN LCD frame signal ...
VLINE STN LCD line signal ...
VM STN VM alternates the polarity of the row and column voltage ...
VSYNC TFT: vertical synchronous signal ...
HSYNC TFT: Horizontal synchronous signal ...
VDEN TFT: data enable signal ...
LEND TFT: Line End Signal ...
STV SEC TFT: SEC TFT LCD panel control signal ...
CPV SEC TFT: SEC TFT LCD panel control signal ...
LCD_HCLK SEC TFT LCD panel control signal ...
TP SEC TFT LCD panel control signal ...
STH SEC TFT LCD panel control signal ...
LCDVF[2:0] Timing Control signal for specific TFT LCD ...
E. Interruput Control Unit ...
EINT[23:0] External Interrupt Request ...
F. DMA
nXDREQ[1:0] External DMA Request ...
nXDACK[1:0] External DMA acknowedge ...
G. UART
RXD[2:0] UART receives data input ...
TXD[2:0] UART transmits data output ...
nCTS[1:0] UART clear to send input signal ...
nRTS[1:0] UART request to send output signal ...
UEXTCLK UART clock signal ...
H. ADC
AIN[7:0] ADC INPUT[7:0] if it isn`t used pin , it has to be in Ground ...
Vref ADC Vref
I. IIC-BUS
IICSDA IIC-BUS data
IICSCL IIC-BUS clock
J. IIS-BUS
I2SLRCK IIS-BUS channel select clock ...
I2SSDO IIS-BUS serial data output ...
I2SSDI IIS-BUS serial data input ...
I2SSCLK IIS-BUS serial clock ...
CDCLK CODEC system clock ...
K. TOUCH SCREEN
nXPON Plus x-axis on-off control signal
nXMON Minus x-axis on-off control signal
nYPON Plus y-axis on-off control signal
nYMON Minus y-axis on-off control signal
L. USB HOST
DN[1:0] DATA(-) from usb host ...
DP[[1:0] DATA(+) from usb host ...
M. USB DEVICE
PDN0 DATA(-) for usb peripheral
PDP0 DATA(+) for usb peripheral
N. SPI
SPIMISO[1:0] Master data input line,when spi is configured as a master .When spi is configured as a slave , these pins reverse its role .
SPIMOSI[1:0] Master data ouput line,when spi is configured as a master. When spi is configured as a slave ,these pins reverse its role .
SPICLK[1:0] SPI clock ...
nSS[1:0] SPI chip select ...
O. SD
SDDAT[3:0] SD receive / transmit data .
SDCMD SD receive / transmit command .
SDCLK SD clock .
P. General Port
GPn[116:0] general input/output ports . Some ports are output only .
Q. TIMMER/PWM
TOUT[3:0] Timer Output[3:0] .
TCLK[1:0] External timer clock input .
R. JTAG TEST LOGIC
nTRST nTRST reset the TAP controller at start . If debugger is used , a 10k pull-up resistor has to be connected . If debugger is not used , nTRST must be issued as a low active pulse ...
TMS TMS control the sequence of the TAP controller`s states . A 10k pull-up resistor has to be connected ...
TCK provides the clock input for the JTAG LOGIC ... A 10K pull-up resistor has to be connected ...
TDI the serial input for test instruction and data . A 10K pull-up resistor has to be connected ...
TDO the serial output for the test instruction and data .
S. Reset , Clock & Power ...
nRESET suspends and operation in progress and places s3c2410 into a known reset state . For a reset , nRESET must be held to level for at least 4 FCLK after the processor power has been stabilized .
nRSTOUT For external device reset control .
PWREN 2.0v core power on-off control signal .
nBATT-FLT Probe for battery state . Does not wake up in power-off mode in case of low battery state . If it isn`t used , it has to be high (3.3v) .
OM[3:2] determines how the clock is made .
EXTCLK external clock source .
XTIPLL Crystal input for internal osc circuit .
XTOPLL crystal output for internal osc circuit .
MPLLCAP loop filter capacitor for main clock .
UPLLCAP loop filter capacitor for USB clock .
XTIrtc 32.768khz crystal input for RTC .
XTOrtc 32.768khz crystal output for RTC .
CLKOUT[1:0] clock output signal .
VDDalive S3C2410A reset block and port status register (1.8v / 2.0v)
VDDi/VDDiram S3C2410A core logic VDD (1.8v/2.0v)
VDDi_MPLL S3C2410A MPLL analog and digital VDD (1.8v/2.0v)
VSSi_MPLL S3C2410A MPLL analog and digital VSS
VDDOP S3C2410A I/O port VDD(3.3v)
VDDMOP S3C2410A Memory I/O VSS
VSSOP S3C2410A I/O port Vss
RTCVDD RTC Vdd (1.8v , not support 2.0v / 3.3v )
VDDi_UPLL S3C2410A UPLL analog and digital VDD
VSSi_UPLL S3C2410A UPLL analog and digital VSS
VDDA_ADC S3C2410 ADC VDD(3.3V)
VSSA_ADC S3C2410 ADC VSS
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