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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vhdl2 IS
generic(n:integer:=2000);
PORT(
CLK: IN STD_LOGIC;
CLKOUT_3:BUFFER STD_LOGIC
);
END vhdl2;
ARCHITECTURE A OF vhdl2 IS
SIGNAL CNT1,CNT2:integer:=0;
SIGNAL OUTTEMP:STD_LOGIC;
SIGNAL LOUT:STD_LOGIC;
SIGNAL OUT3:STD_LOGIC:='0';
BEGIN
pROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF CNT1=n-1 THEN
CNT1<=0;
ELSe
CNT1<=CNT1+1;
END IF;
END IF;
END PROCESS;
pROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='0'THEN
IF CNT2=n-1 THEN
CNT2<=0;
ELSE
CNT2<=CNT2+1;
END IF;
END IF;
END PROCESS;
pROCESS(CNT1,CNT2 )
BEGIN
if ((n mod 2)=1) then
IF CNT1=1 THEN
IF CNT2=0 THEN
OUTTEMP<='1';
ELSE OUTTEMP<='0';
END IF;
ELSIF CNT1=(n+1)/2 THEN
IF CNT2=(n+1)/2 THEN
OUTTEMP<='1';
ELSE OUTTEMP<='0';
END IF;
ELSE
OUTTEMP<='0';
END IF;
else
if cnt1=1 then
outtemp<='1';
elsif (cnt1=(n/2+1)) then
outtemp<='1';
else
outtemp<='0';
end if;
end if;
END PROCESS;
pROCESS(OUTTEMP,clk)
BEGIN
if ((n/=2) and (n/=1)) then
IF OUTTEMP'EVENT AND OUTTEMP='1' THEN
CLKOUT_3<=NOT CLKOUT_3;
END IF;
elsif (n=2) then
if(clk'event and clk='1')then
clkout_3<=not clkout_3;
end if;
else
clkout_3<=clk;
end if;
END PROCESS;
END A;
系统分类:
CPLD/FPGA | 用户分类:
CPLD/FPGA | 来源:
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