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发表于:2009/6/20 22:34:21
标签:ATA协议  

0

如何阅读ATA-5协议文档

    ATA-5标准规范文档(下文简称ATA-5文档)是我工作以后用到的第一份比较全面而复杂的标准文档。这份文档,在我第一份工作近三年的时间内被我反复的阅读和使用。在它的指导下,我完成了一款ATA设备端产品的维护、升级和另一款新产品的开发。正如对自己的第一份工作怀有深厚的感情一样,对ATA协议,我也一直在关注着它的发展变化。 riple
    最近在“ATA协议A、B、C”小组看到有网友说看了ATA标准规范文档后不知道从何入手,这一困惑我也曾经有过。在这篇文章里,我就尝试着把ATA-5文档的大致结构捋一下,把文档中我熟悉的重点和难点部分标示出来。 riple

    ATA-5文档共分10个条款:

条款1 描述了文档内容涉及的范围。 riple
条款2 提供了文档参考的其他规范。 riple
条款3 提供了文档中用到的名词定义、缩写定义和文档格式约定。 riple
条款4 包括了PATA接口的电气和机械特性。 riple
条款5 包括了PATA接口的信号描述。 riple
条款6 描述了ATA接口的概要的操作要求。 riple
条款7 包括了ATA接口的寄存器描述。 riple
条款8 包括了ATA接口的命令描述。 riple
条款9 包括了ATA接口的协议描述。 riple
条款10 包括了接口的时序图。 riple
    条款4、5是物理规范部分,描述了PATA设备的接口特性,是进行物理设计的参考;条款的7、8、9、10是逻辑规范部分,描述了ATA设备的行为特性,是进行逻辑设计的参考;条款6是对ATA设备特征的一个概述,为后面4个章节做了铺垫。 riple

    ATA-5文档是从规范性和兼容性角度描述PATA协议的,内容是详细完整而自洽的。文档的内容包含了完成主机端或设备端硬件和软件设计的所有规范。但是,从设计实现的角度看,文档的结构并不适合顺序地逐章阅读,原因是每一个条款的内容都很丰富,对于初次接触文档的读者来说,由于对协议的整体框架和ATA接口要实现的功能没有整体的把握,很难理解每一个条款对于设计实现的意义所在,很难把文档的具体内容与设计实现过程中的各个主题联系起来,很容易看了前面,忘记了后面,反复多次通读文档才能逐渐有所收获。 riple

    如果按照如下的顺序阅读ATA-5文档,就比较容易掌握文档的结构:
    0. 在网络上查找对ATA接口的通俗解释和说明,弄清ATA接口的基本用途和功能。 riple
    1. 通读条款3,不要求对内容记忆深刻,只要求掌握条款3的结构,记得条款3都说过哪些内容即可。这么说,并不代表条款3的内容不重要;相反,条款3是最重要的,在对文档整体熟悉后,进行设计实现时,必须按照条款3的要求对后续条款字斟字酌。由于条款3是为后续条款服务的,所以只有在阅读后续条款时它才有意义。在阅读后续条款的过程中遇到问题时再返回条款3来查找,几次之后就烂熟于心了。 riple
    2. 精读条款6,选读条款8。精读条款6的目的是明确ATA设备都具备哪些功能,为后续条款的阅读做准备。精读要根据自己的设计实现要求有侧重点地进行。比如只要求实现PIO,那么就可以略过DMA的相关内容;比如只要求兼容ATA,那么就可以略过ATAPI相关的Packet命令。初次阅读略过的内容,可以在基本协议实现后,返回来阅读。可以不阅读6.7以后的各个小节。 riple
    精读条款6的6.4小节,就可以确定设计实现必须要实现的基本命令集,明确设计目标,也明确了后续条款的阅读目标。在此过程中,要参考条款8中各条命令的描述部分,以明确各条命令的意义。在阅读完6.4小节之后,需要生成一个列表,该列表包括了要实现的所有命令及其对应的协议。命令和协议的对应关系可以通过附录中的表格F.3获得。 riple
    3. 精读条款4和5。这两章,对PCB设计和FPGA引脚约束(位置、电平、电流强度)是至关重要的。这是整个板级设计成功的保证。没有稳定的物理接口这个基础,FPGA实现和调试是不可能顺利的。这两个条款不要求反复阅读,只要求在PCB设计确定前读透读明白。对于FPGA设计者来说,UDMA相关的内容可以在初次阅读时略去,在实现MDMA基本功能后返回来阅读;对PCB设计者来说,出于兼容性设计的考虑,UDMA相关的内容应该尽量读明白。 riple
    4. 精读条款9、8、7。要按照“先协议、后命令、最后寄存器”的逆序进行。协议是一类命令的共同行为特性,掌握了一个协议,就可以掌握一类命令;明白了命令的输入和输出,就可以弄明白为什么要设置这些寄存器和寄存器的位意义。要打破条款的自然章节划分,按照协议及相关的命令和寄存器纵向阅读。比如9.4小节的non-data命令协议对应了28条命令,所有这些命令都遵循同一个协议规定的简单行为;8.37小节的SET FEATURES命令属于non-data协议,8.37.8给出了该命令的描述,8.37.9 - 8.37.20给出了该命令的子命令介绍,8.37.4和8.37.5给出了该命令对应的输入输出寄存器;大部分寄存器的内容都是命令相关的,所以条款7必须结合着条款8阅读才有意义;附录中的表格F.4给出了寄存器与物理引脚之间的关系。 riple
    明确了协议-命令-寄存器-引脚之间的关系,就可以着手进行逻辑实现了。 riple
    5. 通读条款10。这是对第一次阅读文档的要求。在进行逻辑实现时,必须详细阅读这一条款,明确主机与设备之间的物理握手,并明确各个时序参数该如何在具体设计中得以实现。 riple

    条款1、2没有什么实际内容,可以略去不读;附录的6个小节中包含了重要的信息和表格,需要深入阅读和反复参考。 riple


相关链接:
如何下载ATA协议文档

系统分类: CPLD/FPGA   |    用户分类:    |    来源: 原创

该用户于2009/6/21 17:09:46编辑过该文章

评论(4) | 阅读(252)
发表于:2009/6/18 18:55:04
标签:Ubuntu  ns2  ns3  

0

如何在Ubuntu 8.04下安装ns-2和ns-3

安装ns-2:
在ns-2的wiki上有一个网页专门介绍如何在Ubuntu 7.04下面安装ns-2,在Ubuntu 8.04下面也可以按照相同的步骤进行。需要注意的是,通过apt-get下载安装必要的软件包之前,需要更新Ubuntu的apt-get网址列表:
sudo apt-get update
sudo apt-get upgrade
然后就可以按照wiki网页上的操作步骤进行了。

安装ns-3:
在ns-3的wiki上有一个网页专门介绍如何安装ns-3及所需的软件包。这里给出的软件包安装步骤过于复杂,其实只需要安装flex和bison就可以完成ns-3的安装了。在google上面有一个ns-3的小组,里面有一篇讨论就给出了Ubuntu8.04下安装ns-3失败的解决方案
sudo apt-get install flex bison
同样地,还是先要更新apt-get的网址列表。

总结一下:
1. 下载ns-2/3安装包
2. 更新Ubuntu的apt-get网址列表
3. 下载并安装必要的软件包
4. 安装ns-2/3

国内还没有介绍ns-3的书出版,介绍ns-2的有几本。ns-2使用Tcl语言进行仿真控制(Tcl的面向对象扩展:OTcl),ns-3使用Python或C++进行仿真控制,如果只是仿真的话,语法并不复杂,照葫芦画瓢即可。如果需要扩展ns-2或ns-3,都需要C++,都需要用到OOP。如果需要深入学习的话,还是从ns-3开始比较好。一是因为www.nsnam.org上有针对ns-3丰富的教程和说明,更新维护都比较及时;二是因为ns-3抛弃了OTcl捆绑C++的方式,转向了Python捆绑C++的方式,甚至可以完全用C++进行仿真控制和扩展编程,语言比较单一,学习难度就降低了。
我是刚刚开始学习,学多少卖多少,再多的就不知道了。

相关链接:
Jason的CS博客 实践者的足迹

ns-2教程:

NS by Example

Marc Greis' Tutorial for the UCB/LBNL/VINT Network Simulator "ns"


ns-3教程:

ns-3 tutorial: ns-3 Tutorial (html version)


系统分类: 通信网络   |    用户分类:    |    来源: 原创

该用户于2009/6/18 19:02:23编辑过该文章

评论(0) | 阅读(246)
发表于:2009/6/16 12:31:06
标签:ATA协议  

0

如何下载ATA协议文档

下载ATA协议,就要到T13的官网上。T13是什么意思?我不知道。只知道有一个T10是管SCSI的,还有一个T11是管FC的,T13是管ATA的。这三个Technical Committee都是与存储技术有关的。 riple

T13上面有两类文档:标准(Standards)和草稿(Drafts)。标准都是要收费的,草稿是免费下载的。我们进行设计就可以参考草稿。下载草稿的页面可以从主页上如下的链接进入:Projects -> Last Drafts riple

点击看大图


ATA协议最新的版本是ATA-8ATA-1ATA-3都是废弃的老版本了,ATA-4以后的版本都是有效的。ATA-5应该是一个稳定的,得到广泛应用的版本,许多兼容设计都可以以此版本为参考。ATA-6及之前的版本中,ATA协议就等于PATA协议,各个版本协议的格式基本一致。从ATA-7开始,协议中加入了SATA部分,为了总结SATAPATA协议的异同点,ATA-7协议分成了三卷,卷一、卷二的内容覆盖了以前版本的内容,卷三是针对SATA相关内容而增加的。从ATA-8开始,协议进一步细化为4部分:ATA8-AAMATA8-APTATA8-ASTATA8-ACS。其中,ATA8-ACS相当于ATA-7的卷一(具体协议部分移到了ATA8-AAM中),ATA8-APT相当于ATA-7的卷二,ATA8-AST相当于ATA-7的卷三。ATA8-AAMATA-8中提纲挈领的一卷,在这一文档中,总结了所有ATA实现形式的共性内容,首次提出了ATA协议的分层概念(这有点像是以太网的分层概念),首次提出了ATA协议的“客户端-服务器”模型。 riple

个人认为,ATA8-AAM在ATA协议发展具有里程碑意义。有了AAMATA协议的实现形式就更容易多样化,既有P-ATA,也有S-ATA,还有ATAoE,任何一种实现形式都可以在兼容AAM的前提下自由发展,任何一种实现形式发展到了尽头都可以被抛弃。ATA协议由于抽象出了AAM而得以长葆青春,获得了更广阔的发展空间。 riple

下表拷贝自下载页面,略去了所有与ATA协议主要版本无关的内容。 riple

T13: Last Drafts
Doc. Number Title Author Sub. Date
791Dr4c
791D: AT Attachment Interface for Disk Drives (ATA-1) (Withdrawn 1999)


Larry Llamers 01/01/94

943Dr4c
948D: AT Attachment Interface with Extensions (ATA-2) (Withdrawn 2001)


Stephen G. Finch 03/18/96

2008Dr7b
2008D: AT Attachment - 3 Interface (ATA-3) (Withdrawn 2002)


Pete McLean 01/17/97

1153Dr18
INCITS 317-1998 (1153D): AT Attachment - 4 with Packet Interface Extension (ATA/ATAPI - 4)

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 3 Interface (ATA-3), X3.298-1996, and earlier definitions of the AT Attachment Packet (ATAPI), and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

Pete McLean 08/19/98

1321Dr3
INCITS 340 (1321D): AT Attachment - 5 with Packet Interface (ATA/ATAPI - 5)

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 4 with Packet Interface Extension (ATA/ATAPI-4), 1153D, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

Pete McLean 02/29/00

1410Dr3b
INCITS 361-2002 (1410D): AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6)

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 5 with Packet Interface (ATA/ATAPI-5), 1321D, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

Pete McLean 02/26/02

D1532v1r4b
INCITS 397-2005 (1532D): AT Attachment with Packet Interface - 7 Volume 1

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 6 with Packet Interface (ATA/ATAPI-6), 1410D, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

John Masiewicz 04/21/04

D1532v2r4b
INCITS 397-2005 (1532D): AT Attachment with Packet Interface - 7 Volume 2

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 6 with Packet Interface (ATA/ATAPI-6), 1410D, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

John Masiewicz 04/21/04

D1532v3r4b
INCITS 397-2005 (1532D): AT Attachment with Packet Interface - 7 Volume 3

This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. It includes the Packet Command feature known as the AT Attachment Packet Interface (ATAPI). This standard maintains a high degree of compatibility with the AT Attachment - 6 with Packet Interface (ATA/ATAPI-6), 1410D, and while providing additional functions, is not intended to require changes to presently installed devices or existing software.

John Masiewicz 04/21/04

d1700r3
ATA8-AAM

This standard describes the AT Attachment Architectural Model. The purpose of the architecture model is to provide a common basis for the coordination of ATA standards and to define those aspects of ATA system behavior that are independent of a particular technology and common to all implementations.

Mark Evans 05/28/06

d1698r2
1698D: AT Attachment-8 - Parallel Transport (ATA8-APT)

This standard specifies the AT Attachment Interface between host systems and storage devices using a parallel electrical interface. It provides a common attachment interface for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices.

Mark A. Overby 11/21/07

d1697r1
1697D: AT Attachment-8 - Serial Transport (ATA8-AST)

This standard specifies the serial transport for the AT Attachment Interface between host systems and storage devices. It includes the serial transport Protocols and Physical Interconnect for AT Atachment devices commonly known as Serial ATA.

Curtis E. Stevens 12/12/07

D1699r6a
INCITS 452-2008 (D1699): AT Attachment 8 - ATA/ATAPI Command Set

This standard specifies the AT Attachment command set between host systems and storage devices. It provides a common command set for systems manufacturers, system integrators, software suppliers, and suppliers of intelligent storage devices. It includes the PACKET feature set implemented by devices commonly known as ATAPI devices. This version integrates ANSI Editor and public review comments.

Curtis E. Stevens 09/16/08




相关链接:

Parallel ATA on Wikipedia

Serial ATA on Wikipedia

ATA over Ethernet on Wikipedia

CE-ATA

 

背景知识:

INCITS (InterNational Committee for Information Technology Standards)

INCITS is the primary U.S. focus of standardization in the field of Information and Communications Technologies (ICT), encompassing storage, processing, transfer, display, management, organization, and retrieval of information. As such, INCITS also serves as ANSI's Technical Advisory Group for ISO/IEC Joint Technical Committee 1. JTC 1 is responsible for International standardization in the field of Information Technology.

 

INCITS TECHNICAL COMMITTEES
Languages / Database Media / Education Security / ID Storage Information Services / Office / Text INCITS Executive Board Study Groups

 

系统分类: CPLD/FPGA   |    用户分类:    |    来源: 原创

该用户于2009/6/21 16:50:28编辑过该文章

评论(0) | 阅读(295)
发表于:2009/6/13 23:41:38
标签:FPGA  开发方法学  

0

《基于FPGA的快速系统原型开发》第四章译后记

    《基于FPGA的快速系统原型开发》第四章终于翻译完成了。从4月2日到6月13日,在这两个半月的时间里,我利用晚上和周末的时间,先是手工输入了原文的13个小节,然后逐个完成了各个小节的翻译。
    虽然我通读过原书的各个章节,对第四章还读了两遍以上,但是在翻译过程中仍然发现了许多在先前的阅读中没能理解准确的句子、没有掌握的词汇、未曾接触过的概念。Wikipedia给了我很多帮助,提供了许多“金山词霸在线版”不能提供的背景知识和相关概念。
    正如Amazon上该书的读者评价所说,这本书“对FPGA初学者助益不大”,“对有经验的FPGA设计者来说是一本好书”。尽管如此,我仍然推荐EDNChina上的各位FPGA工程师和爱好者们简单浏览一下该书的这一章。对于初学者来说,即使看不懂、看不透,也能一窥FPGA工程开发的大致过程,也能对以后将要遇到的设计题目有所了解;对于像我这样对FPGA开发有一些实际经验的朋友们来说,通过这章介绍的内容,一是可以加深自己对规范的开发过程的认同,对现在采用的开发方法能够有所改进,查漏补缺,二是可以促进自己对尚未采用的开发方法和原则做进一步的了解。
    曾经对许多译成中文的技术书籍的翻译质量有所不满,直到自己尝试着翻译了这一章,才明白科技英语翻译工作的不易,才意识到对译作者应该多些包容:看得懂是一回事,译得出、译得顺又是另外一回事。我的文字水平不高,实际经验更是不足,对这一章关于FPGA开发系统工程方法学的翻译肯定会存在许多不足和错误,恳请大家批评指正。

    最后,我要呼吁国内的出版社引进该书的版权,出版该书的影印版,最好能够组织对FPGA开发有丰富的实践经验的专家们把该书译成中文版。虽然在国内现有的FPGA设计书籍中,入门书、语法书、技巧书占据了绝大多数,但是随着国内FPGA开发者整体水平的提高和大型FPGA开发项目的增多,像这样一本系统地介绍FPGA工程开发过程和方法的书也一定会广受欢迎。我的一位博士师兄说过,“写好书是积德的”。该书的引进,应该会对我们国内FPGA开发工程师整体水平的提高,对FPGA工程开发质量的提高和工程开发过程的规范化起到促进作用。


《基于FPGA的快速系统原型开发》翻译进度:

《基于FPGA的快速系统原型开发》翻译计划 第四章 系统工程开发方法riple

[译完] Rapid System Prototyping with FPGAs - 4.1 概述riple

[译完] Rapid System Prototyping with FPGAs - 4.2 常见的设计挑战和错误riple

[译完] Rapid System Prototyping with FPGAs - 4.3 明确的FPGA设计过程规范riple

[译完] Rapid System Prototyping with FPGAs - 4.4 工程开发和管理riple

[译完] Rapid System Prototyping with FPGAs - 4.4.1 团队交流riple

[译完] Rapid System Prototyping with FPGAs - 4.4.2 设计评审riple

[] Rapid System Prototyping with FPGAs - 4.4.3 预算和日程安排riple

[] Rapid System Prototyping with FPGAs - 4.5 培训riple

[] Rapid System Prototyping with FPGAs - 4.6 技术支持riple

[] Rapid System Prototyping with FPGAs - 4.7 设计配置管理riple

[] Rapid System Prototyping with FPGAs - 4.7.1在上板调试过程中对FPGA设计进行配置控制riple

[] Rapid System Prototyping with FPGAs - 4.7.2 把设计存档riple

[] Rapid System Prototyping with FPGAs - 4.8 总结riple



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该用户于2009/6/14 9:56:51编辑过该文章

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标签:FIFO  

3

关于FIFO的几个问题——写作计划

最近一段时间的工作中使用FIFO很频繁,思考了一些与FIFO有关的问题,准备写几篇关于FIFO使用方法的文章,总结一下在以往工作中遇到的相关问题。惟恐遗忘,先写几个题目在此。等到把Rapid System Prototyping with FPGAs的第四章翻译完,就开始着手写这几个题目的文章,每一篇都会给出Quartus II的完整工程和Modelsim下的仿真工程。

关于FIFO的几个问题——安全的读空
关于FIFO的几个问题——滞回水位线
关于FIFO的几个问题——无拖尾输出
关于FIFO的几个问题——可变延迟线

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该用户于2009/4/26 19:23:37编辑过该文章

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[译完] Rapid System Prototyping with FPGAs - 4.8

4.8 Summary

This chapter presents the definition of rapid system prototyping as: “The development of system functionality at a pace faster than conventional development with an emphasis on design efficiency while balancing schedule compression activities with project risk.” Rapid prototyping addresses critical time-to-market and budget pressure issues.

       The key system engineering topics and issues identified and addressed in this chapter include:

  • Common design mistakes and oversights
  • Design risk factors
  • Team communication
  • Design review
  • Budget and estimation
  • Training and support
  • Configuration management

       This chapter stresses the importance of a defined, efficient and optimized FPGA design process for rapid system development efforts. It is essential to understand the common design issues and challenges design teams may encounter during a rapid development project. Common design issues and challenges are identified and discussed in this chapter. Having a defined FPGA design process helps reduce the number and impact of design errors on a rapid development project by providing a development control mechanism. Some of the mechanisms that may be put in place to establish and maintain control include design guidelines, official design procedures, configuration control, and design reviews.

       Regular meetings can encourage team communication, which is essential to efficient project progress. Design reviews are important for identifying design issues early in the cycle before they can become difficult to remove or potentially affect project success. Design effort estimation and realistic budget creation are both critical to perceived project success at the management level. Team training can boost team morale and efficiency. Configuration management is a complex, challenging task that is often delayed or eliminated in rapid development efforts. Configuration control is, however, an essential system engineering factor.


4.8 总结

这一章介绍了“快速系统原型开发”的概念:“以比传统开发更快的速度开发系统功能的过程,这一过程以设计效率为着重点,同时还要在日程压缩和项目风险之间保持平衡。”快速原型开发解决了上市时间和预算压力这两个严峻的问题。

这一章指出的和解决的关键的系统工程开发题目和问题包括:

1.         普遍的设计错误和疏漏

2.         设计风险因素

3.         团队交流

4.         设计评审

5.         预算和评估

6.         培训和支持

7.         配置管理

这一章强调了定义清晰的、高效的和优化的FPGA设计过程对快速系统开发工作的重要性。理解设计团队在快速系统原型项目开发过程中可能会遇到的普遍的设计错误和挑战是至关重要的。在这一章中指出和讨论了普遍的设计问题和挑战。定义清晰的FPGA设计过程通过提供一个开发过程控制机制,有助于减少设计错误的数量和减轻设计错误对快速开发项目的影响。可以付诸实施的用以建立和保持对开发过程控制的机制包括,设计指导方针,正式的设计步骤,配置控制和设计评审。

例会可以鼓励团队交流,这对提高项目进展效率是必要的。设计评审对于在设计早期,在设计问题变得难以移除或者潜在地影响项目成功之前发现这些问题是非常重要的。设计工作量评估和切合实际的预算制定,对于管理层评估项目的可行性都是关键的。团队培训可以提高团队的士气和效率。配置管理是一个复杂的,具有挑战性的任务,在快速开发工作中经常会被推迟或者忽略。然而,配置控制是系统工程开发中必不可少的一个因素。

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该用户于2009/6/14 8:50:43编辑过该文章

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[译完] Rapid System Prototyping with FPGAs - 4.7.2

4.7.2 Archiving the Design

After the project has been completed, but before the design team is reassigned, a project design archiving should be generated. A complete archive should include all the functionality listed for a complete configuration version backup plus the source disks for all essential software tools, all software patches, design updates, known tool issue work-arounds, tools, design estimates including schedule, manpower and budget, manufacturers documentation, and all other technical content or effort associated with the development effort. The archived design should include all files required to implement a version of the design in the future, including a version of the OS (with installed patches) and all hardware and software keys. For completeness, all design notes, board layout files, development and production documentation and databases, component datasheets, user’s guides and component errata should also be included. By definition, at the end of a project all the information and knowledge required to implement that project should be readily available. As the years pass, much of the information will cease to be available and access to the original design team will also be reduced. The budget to completely archive a design should be set aside in management reserve when a project is started. If there is any significant possibility the design will need to be updated or leveraged in the future, the investment in wrapping up a design immediately after it is completed will likely be exponentially less than it will be at any time in the future. A summarized list of design archive content for a design is shown in the following list.

Design Archive Considerations

  • Design hierarchy
  • Design file descriptions and relationships
  • A script file which automates all or part of the design build sequence
  • All source files required to reconstruct the final versions of the design
  • Clearly identified final versions of all files to eliminate ambiguity
  • A list of all design tools, version numbers, revision states
  • All design tool license files, hardware keys and license installation instructions
  • The original source media for all design tools and revision updates (no dependency on the internet, internal computer network or specific computer for any files)
  • Complete final design source and output file database with clearly identified final file versions
  • Hardware equipment version number required to download and interface to the target board
  • Design Flow Documents including: A documented procedure/process for converting and downloading the placed and routed design to the target board with step-by-step instructions and required tool settings
  • Source code and documentation for all IP utilized in the design
  • Tools required to implement and integrate IP functions within the design
  • IP license agreements, keys and software key installation procedure
  • A golden design disk containing the critical source files and clearly labeled final FPGA image file(s)
  • A clearly and completely documented design build sequence
  • Design documents including the final version of: unit operation manual, final board schematics (including white-wires and board modifications), design integration, test plans, requirements, testing procedures, and verification matrix, and design review documents

A complete design archive can be trusted only when the entire load sequence has been verified on an unconfigured computer (preferably including the loading of the PC’s operating system and any patches or updates required to support the FPGA design tool operation). This may take several hours but will identify any missing source data or documentation at a time when fixing the problem will be cheaper than at any time in the future.

Verify and re-verify the FPGA I/O signal assignments against the PCB FPGA schematic symbol. Ideally, a final cross check should be done between the final post layout and route FPGA report files and the final PCB board netlist. It is possible there may have been some back and forth FPGA pin changes during the PCB layout process, however, after the PCB has been released to be fabricated no more FPGA I/O assignment changes can be made. While every effort must be made to make sure that the I/O assignments don’t change (usually the I/O assignments are located within a design constraint file) the final PCB release I/O assignments should be documented and again verified before the first FPGA device image is downloaded to the target hardware board. If the pin assignments within the FPGA do not agree with the implemented design at the board level, damage can occur to either the FPGA component or the board-level circuits.


4.7.2 把设计存档

项目完成后,设计团队分配新任务前,需要对项目的设计进行归档。最基本的归档应该包括通过配置控制(版本控制)工具取得的功能完整的版本的备份,加上所有关键软件工具的安装盘,所有的软件补丁,设计更新,已知问题的处理措施、工具,包括日程、人力和预算在内的设计评估文档,厂商文档,和所有其它与开发过程有关的技术内容或开发成果。设计归档应该包括在未来重现该设计某一个版本的所有必需的文件,包括操作系统的一个版本(安装了补丁)和所有的硬件“狗”和软件安装序列号。为了归档的完整性,还应该包括所有的设计笔记,电路板版图文件,开发和生产文档和数据库,器件数据手册,用户指南和器件勘误表在内。在项目完成时,所有用以实现该项目的必需的信息和知识自然都是齐备的。但是几年过去之后,许多信息就很难找得到了,原有的设计团队也越来越不容易接触得到。当项目启动时,就应该分配预留的经费用以对设计进行完整的归档。如果在未来有对该设计进行更新和利用的显著的可能性的话,在设计完成之际对设计归档所需的投资比在未来任何时候对设计归档所需的投资都会成指数减小。下面的列表总结了设计归档所需的内容:

设计归档考虑因素

1.         设计的层次结构

2.         设计文件内容和相互关系的描述

3.         用以自动化顺序构建部分或全部设计的脚本

4.         重建设计最终版本所需的全部源文件

5.         定义明确的所有文件的最终版本号,以消除歧义

6.         设计工具列表,及其版本号,修订状态

7.         所有设计工具的许可文件,硬件“狗”和许可文件安装说明

8.         所有设计工具的原始安装媒体和修订更新(任何文件都不能依赖于互联网、内部计算机网络、或特定的计算机来获得)

9.         设计源文件和输出文件完整的最终数据库,这些都需要有一个明确的最终版本号

10.     对目标板下载和连接所需的硬件设备的版本号

11.     设计流程文档,包括:记录在案的对布局布线后的设计进行转换和下载至目标电路板的程序/过程,应该包含详细的操作步骤和必要的工具设置

12.     设计中用到的所有IP的源代码和文档

13.     在设计中实现和集成IP功能的必需的工具

14.     IP授权协议,硬件“狗”和软件序列号安装程序

15.     一个包含关键源文件和标示明晰的最终FPGA映像文件的“金质”设计光盘

16.     一个清晰完整的设计构建次序文档

17.     所有的设计文档,包括最终版本的产品操作手册、最终电路原理图(包含飞线和电路板更改),设计集成和测试计划,需求文档,测试步骤和验证列表,设计评审文档

只有在一台“干净”的(未经配置的)计算机上(最好重新安装PC机的操作系统和用以支持FPGA设计工具操作的必要的补丁或更新),对整个加载流程进行了验证,一个完整的设计归档才是可以置信的。虽然这么做会花费数个小时,但是通过验证可以发现任何缺失的源数据或文档,这时修复这些问题花费的代价比在将来任何时候都要小。

反复验证FPGAI/O信号分配与PCB上的FPGA封装符号是一致的。理想的情况下,最终的交叉检查应该在最终的FPGA布局布线后报告文件和最终的PCB网表之间进行。在PCB版图设计过程中,有可能会有一些反复的FPGA引脚变更,但是,当PCB发布并送交生产后,就不能对FPGAI/O分配进行任何修改了。在确保I/O分配不发生变化的同时(通常I/O分配会保存在一个设计约束文件中),最终发布的PCB上的I/O分配也应该归入文档,并在第一次下载FPGA映像文件到目标电路板之前,再次进行验证。如果FPGA上的引脚分配与在电路板一级实现的设计不符的话,就会损坏FPGA器件或电路板上的外围器件。

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该用户于2009/6/13 10:27:39编辑过该文章

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[译完] Rapid System Prototyping with FPGAs - 4.7.1

4.7.1 Controlling the FPGA Design in the Lab

With the freedom to change, recompile and reload the FPGA design to a board comes the responsibility to keep track of changes and keep FPGA design versions under configuration control. It is not enough to always have access to the latest design FPGA version. Occasionally it may be necessary to go back ten or more versions of the FPGA design to revisit a specific problem or subsequent fix. This can only be accomplished if versions of the FPGA design are well documented and carefully stored away for future retrieval. Board configuration control factors are listed below.

  • FPGA design files must be kept under configuration control so that any specific build can later be recreated
  • Different FPGA design chains or “trees” may need to be maintained for different board versions
  • This requires an efficient, effective way of propagating design updates made in one design chain to all current operational FPGA designs
  • Design versions should include built-in documentation of the design change history including:
  • Change description, reason for change and who made the change, current revision of the design, date, time, etc

       This responsibility is further complicated when multiple versions of the target hardware exist, which require different versions of the FPGA design. For example, if a board update to a hardware design requires swapping an input and output between two FPGA pins, the FPGA versions for the modified board will have to be different than those loaded onto the unmodified board. Loading the wrong FPGA version to a board could result in unpredictable behavior or component damage. By careful FPGA design configuration management and part programming and tracking, serious problems can be avoided.

       Once the FPGA design has been captured and compiled and initially downloaded to the HW target, configuration tracking needs to be maintained at the board level in the lab. Efficient real-world debugging is much easier when as many variables as possible are removed when trying to determine the source of a problem.

       Logbooks should be maintained with each prototype board and these logs should be kept up-to-date. Information in the logbooks should include detailed information when a problem is encountered. What version of the software is running a test? Which board was the test run on? Who ran the test? What host unit was the board installed in? What test equipment was attached to the board? What version was loaded into the FPGA? What was the white-wire configuration of the board at the time of the test? Was the problem consistent or intermittent? What system settings or specific sequence of events seem to affect the occurrence of the problem? Obviously these are difficult things to keep track of, but if this information is accurately recorded and good configuration control is implemented, it should be possible to re-create specific problem configurations, which can be invaluable in tracking down problem sources and testing subsequent solutions.

       Keeping track of the state of the board and other system variables can be just as important as knowing what version of the FPGA was loaded at the time of a specific fault or failure. In other words, when a problem occurred did it have the latest group of hardware modifications? Was it running older controller code? Had the board just returned from rework and not been fully tested? The answers to these questions can help identify system problem sources.


4.7.1 在上板调试过程中对FPGA设计进行配置控制

FPGA设计可以自由地加以改变、重新编译和重新加载到电路板上,由此而来的责任是记录变更和保持FPGA设计的版本在配置控制之下。总是能够得到最新的FPGA设计是不够的。偶尔会有必要回退十个甚至以上的FPGA设计版本来再现某个具体问题及随后相应的解决方法。只有对FPGA设计进行归档并小心保存以备将来检索才能实现上述目标。下面列举了板级配置控制的因素:

1.         FPGA设计文件必须保持在配置控制之下,这样才能在以后重建任何构建

2.         针对不同的电路板版本,需要维护不同的FPGA设计版本链或 “版本树”

3.         这就需要一个高效、有效的方法来把针对一个设计版本链进行的设计更新传递到所有当前可以使用的FPGA设计之中

4.         设计的各个版本中应该包括内建的设计变更历史文档

5.         历史文档应当包括:改变的描述,改变的原因,谁做出了改变,当前的版本、日期、时间等等

当存在目标板的多个版本时,相应地就需要FPGA设计的多个版本,记录变更和配置控制的任务就变得更加复杂了。例如,当电路板设计修改后需要交换FPGA两个引脚的输入输出关系,那么针对新旧两款电路板就会存在不同的FPGA版本。下载错误的FPGA版本到电路板上会导致不可预知的行为或器件损坏。通过谨慎的FPGA设计配置管理和谨慎的器件编程和跟踪,是可以避免严重问题出现的。

FPGA设计完成了设计捕获、编译并第一次下载到了目标电路板上,就需要在实验室中开始维护板级配置跟踪文档。当试图确认问题的源头时,尽可能多的排除可变因素,就更容易实现高效的实际调试。

针对每一个原形电路板都要维护一个日志记录,这些日志要保持更新。日志记录中的信息应该包括问题发生时的详细信息。运行的测试软件是什么版本?测试是在哪个板子上运行的?测试是由谁运行的?板子安装在了哪个主机单元上?板子上附接了什么测试设备?FPGA中加载了什么版本?测试时板子上的飞线(white wire)连接方式是怎样的?问题是持续出现还是偶然出现?怎样的系统设置或具体的事件序列看上去会影响问题的出现?显然,上述信息是很难在事后靠记忆整理追溯的,但是如果这些信息在日志中记录得准确而且实现了很好的配置控制,应该有可能重现具体问题发生的配置环境。能够重现配置环境,对于查找问题的源头和测试相应的解决方案是非常宝贵的。

记录具体故障和失败发生时板子的状态和其它的系统变量就和清楚加载了哪个FPGA版本一样重要。换言之,当问题发生时,对板子是否进行了最近的一组硬件修改?是否运行了老版本的固件代码?板子是否刚刚返工回来,还没有进行全面的测试?对这些问题的回答有助于确认问题的源头。

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该用户于2009/6/13 10:28:33编辑过该文章

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[译完] Rapid System Prototyping with FPGAs - 4.7

4.7 Design Configuration Management

From a management point of view, the primary objectives of configuration control are:

  • Allow the design team to return to a previous version of the design at any point in the previous history of the project
  • Allow the design team to know what changes and updates were made to the design between design versions
  • Allow the design team to undo design updates, recover from database corruptions and computer failures
  • Support having the entire team working with the same version of the design files

All configuration control version backups should include:

  • All design files sufficient to recreate/reconstruct/regenerate the design
  • The hierarchy of all files
  • Any support files such as design build sequence and dependency notes and script files which automates the FPGA build process
  • The path to and contents of any utilized support design library
  • The current version and revision level (software patch) for any software tools used
  • When the design is “archived” at the end of the project, additional design elements that are readily available to the design team should also be included in the collected database

Configuration control and management of a complex FPGA project can be an overwhelming task and is often overlooked due to its complexity. Configuration management provides the ability to accomplish two main functions: the ability to recover from design or file corruption and the ability to go back to a previous point in the design cycle even when the files have not been corrupted.

In some cases, individual designers may go out of their way to limit or avoid configuration control because they perceive it as an unnecessary burden or a drag on design efficiency. Configuration control is a critical path of an efficient repeatable design cycle. Configuration control provides access to the design files required to go back to previous versions of the design if elements of the design become corrupted. Configuration management also improves a new design team’s ability to rebuild the project and update a design after production, when the original design team is no longer available.

Another advantage is the ability to develop better internal estimation methods for future projects. In order to evaluate a project’s progress and challenges, it is important to have access to an accurate record of the design database during the full course of the design. There are many considerations associated with maintaining a design database configuration control process. Following is a list of important configuration control considerations and issues that should be addressed by project management decisions in order to implement a comprehensive configuration management process.

Configuration Control Observations

  • Configuration control for FPGA design can be more challenging because of the many file types and complex file interactions that differ between tool sets and FPGA manufacturers
  • Many design teams do not take the time to clean older unused files out of active directories
  • If design files are not regularly managed and cleaned out, directories can swell to unmanageable sizes
  • Many design teams do not develop a directory structure that is inherently configuration-friendly
  • There are few 3rd party stand-alone configuration control tools targeting FPGA design
  • Many FPGA tools do not have robust full featured built-in configuration control functionality
  • In general the configuration control solutions available for FPGA designs lag behind the functionality and features available in commercial software configuration control software
  • Some FPGA tool sets support limited interface with commercially available 3rd party software configuration control tool suites, but few are fully integrated

One of the biggest challenges associated with FPGA configuration control is making the required difficult and sometimes complex decisions. Making these decisions is easier with the understanding that any configuration control process or plan that is actually implemented is infinitely better than a detailed plan that goes un-implemented, or no configuration control effort at all. Some of the decisions and suggestions to be considered are presented in the following lists.

Configuration Control Decisions

  • Are the selected design tool configuration control features good enough?
  • How frequently should the design be backed up?
  • What constitutes a sufficient backup trigger event? Weekly? Major design updates? Etc.
  • How will major and minor design “versions” be numbered, tracked and stored?
  • What directory structure should be implemented to simplify the backup process?
  • Should “all” the files be backed up every time?
  • If only “source” files are backed up, which ones are they? How can they be tracked?
  • Which team member will be responsible for implementing and verifying that backups have occurred?
  • How often will the ability to re-implement a design be verified using only the saved files?

Configuration control for an FPGA design is in some respect a more complex challenge than configuration control for a conventional processor project. The file types and relationships are more complex and more proprietary than with conventional programming relationships. Manufacturer tools do not currently implement FPGA design configuration control solutions with the same level of features and ease-of-use of programming configuration control solutions. Third-party development tools may implement better configuration control solutions for certain FPGA manufacturers. Following are some configuration control suggestions.

Configuration Control Suggestions

  • Set aside schedule and budget to verify that all files required to rebuild the design from scratch are included in the design backup at least once
  • Make sure that, as new source design files are added to the design, they are included in all subsequent backups (If possible automate this process based on hierarchy or file extension types)
  • Make sure that the configuration backup maintains the relative path/directory structure
  • Keep all required files under a common directory structure since it is generally easier to “roll-up” a directory hierarchy
  • If outside library directories are used, make sure to include those in the backup if they are regularly updated
  • Make informed decisions (and policy) to determine the file directory hierarchy for the design rather than simply letting an ad-hoc directory structure develop. File hierarchies are very difficult to change mid-project
  • Set up a file hierarchy that can easily expand and adapt throughout the life of the project
  • Develop and adhere to a common, agreed-on file-naming convention to be used by the entire design group
  • Develop and adhere to a common agreed on signal naming convention to be used by the entire design group
  • If possible use the same (or very similar) names at the PCB/board level and FPGA top-level
  • If possible use the same (or very similar) names at lower FPGA module levels as used at the FPGA top level
  • If the names do not match, develop and maintain a level-to-level signal translation (relationship) table or database
  • If files are shared between designs, consider making local directory copies so that each design is complete and independent
  • If common design files must be maintained between projects, manage changes very carefully to common files and make sure to include the files in design backups
  • A simple configuration control approach can consist of simply zipping all the appropriate design directories (maintaining the file path hierarchy)

 

4.7 设计配置管理

(译者注:在下文中,“配置控制”可以等价于“版本控制”,但是“配置管理”的概念大于版本控制包含的内容)

从管理的角度看,配置控制的首要目标是

1.         让设计团队可以回退到项目历史上任何一点对应的设计的先前版本上

2.         让设计团队可以获悉在设计版本之间对设计做了哪些改变和更新

3.         让设计团队可以撤销对设计的更新,可以在数据库崩溃或计算机宕机后恢复工作

4.         让整个团队可以工作在设计文件的同一版本上(而不发生冲突)

所有配置控制的版本备份应该包括

1.         所有的设计核心文件,从这些文件足以重新创建和生成完整的设计

2.         所有文件的层次结构

3.         所有的支持文件,比如设计构建的顺序和依赖性记录和自动化FPGA构建过程的脚本

4.         用到的任何设计支持库的路径和内容

5.         使用过的任何软件工具的当前版本和修订级别(软件补丁)

6.         当项目结束时对设计进行归档时,对设计团队来说是随手可用的额外的设计元素也应该包括在已被收藏的数据库中

对复杂的FPGA项目的配置控制和管理,是一项意义重大,具有压倒性的任务,但是由于其复杂性而常常被忽视。配置管理具备完成两个主要功能的能力:从设计或文件损坏中恢复的能力,和回退到设计周期中某个先前点的能力。后一种需求即使在文件没有损坏的情况下也是存在的。

在某些案例中,个别的设计者会特意限制或避免使用配置控制,因为他们把配置控制看作是一个不必要的负担或是设计效率的拖累。配置控制是高效的可重复的设计周期中的关键路径。配置控制提供了在设计元素损坏需要回退到设计先前版本时访问所需文件的通道。在设计投产后,接触不到原有的设计团队的情况下,配置管理也提高了新设计团队重构和更新设计的能力。

另外一个益处是可以通过配置控制制定更佳的对未来项目的内部估计方法。为了评估一个项目的进展和曾经遇到的挑战,能够获得设计数据库在设计全程中变化的精确记录是很重要的。

维护设计数据库的配置控制过程的相关考虑因素很多。为了实现一个全面的配置管理过程,一些问题需要项目管理者做出决定来解决。下面就是在维护一个配置控制过程中重要的考虑因素和需要解决的问题的清单:

配置控制重点问题列表

1.         针对FPGA设计过程的配置控制会更富挑战性。这是因为涉及到众多的文件类型,并且这些文件的复杂交互关系在不同工具集和FPGA厂商之间也有所不同

2.         许多设计团队没有花时间清理活跃的文件目录中无用的旧文件

3.         如果不对设计文件进行定期的管理和清理,文件目录就会不断膨胀以致无法管理

4.         许多设计团队没有制定本质上是配置友好的文件目录结构

5.         缺乏针对FPGA设计开发的独立的第三方配置控制工具

6.         许多FPGA设计工具缺乏稳健的全功能内建配置控制功能

7.         FPGA设计可用的配置控制解决方案提供的功能和特性整体上落后于商用的软件配置管理工具

8.         有些FPGA设计工具提供对市售的第三方软件配置管理工具套件的接口,但是功能有限,更没有能够做到全面集成的

FPGA配置控制面临的最大挑战之一是做出必需的困难和复杂的决定。如果能够明白任何付诸实现的配置控制过程或计划都远比虽然详细但是没能实现的计划好得多,更远胜于没有任何配置控制的过程,那么做出这些决定就容易多了。下面的清单给出了需要加以考虑的决定和建议:

配置控制决定

1.         选用的FPGA设计工具自带的配置控制特性是否足够好?

2.         设计备份的频率是怎样的?

3.         在何时和那些情况下需要进行新的备份?一周一次?主要的设计更新?或是其他?

4.         主要和次要的设计版本如何编号、记录和存放?

5.         怎样设计文件目录结构来简化备份过程?

6.         每次备份都要针对全部的文件进行吗?

7.         如果只需要对源文件进行备份,如何确定它们的类型?如何记录它们的变化?

8.         由谁来负责实现备份?由谁来验证备份的有效性?

9.         备份文件的完整性,即仅通过备份文件来重新实现设计的能力,需要多长时间验证一次?

针对FPGA设计的配置控制在某些方面是比传统的基于处理器的项目的配置控制更复杂的挑战。文件类型更加复杂,与传统的软件或嵌入式编程相比,文件关系更具专有性。FPGA厂商提供的工具中实现的配置控制方案在功能和易用性上还未能达到软件编程中采用的配置控制方案的水平。第三方开发工具对某些FPGA厂商可能实现了更好的配置控制方案。下面是一些配置控制建议:

配置控制建议

1.         分配时间和预算来至少一次验证所有从头重建设计的必需文件都包含在备份中

2.         确保设计中新添加的源文件及时被包含进随后的备份中(有可能的话,基于层次结构或文件类型扩展名来自动化这一过程)

3.         确保配置备份保持了文件的相对路径和目录结构

4.         把所需的文件放置在统一规划的目录结构下,这样做通常使得建立层次化的目录结构更容易

5.         如果使用了外部库文件,确保在备份中包含这些库文件,以防外部库文件更新后找不到原有的库文件

6.         制定广泛获悉的决定(和方针)来确定设计的文件目录层次,而不是简单地放任一个即兴的目录结构随意发展。在项目进行到一半的时候,就很难对文件的层次结构进行变更了

7.         文件目录的层次结构在项目的生命周期中应该建立得具备可扩展性和适应性

8.         制定并坚持统一的共识的文件命名约定,确保全体设计成员使用之

9.         制定并坚持统一的共识的信号命名约定,确保全体设计成员使用之

10.     尽可能在PCB板级和FPGA顶层采用相同或相似的信号名称

11.     尽可能在FPGA底层和FPGA顶层采用相同或相似的信号名称

12.     如果不能做到上述的统一命名,那么就制定并维护一个层与层之间的信号名称(关系)对照表或数据库

13.     如果文件在设计之间共享,考虑建立本地拷贝,确保各个设计是完整和独立的

14.     如果在设计之间必须维持共享的通用文件,那么需要谨慎地管理这些共享文件的变更并确保在设计备份中包含进这些文件

15.     简单的配置控制方法可以由仅仅压缩所有的恰当的设计目录组成(在压缩文件中要保持文件的路径层次)

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