Altera Forum精彩问答汇总

坛中一日，人间数年！

I can't afford losing any of this kind of invaluable information anymore! It is not too late if I start reading and collecting them from now on. I will look the threads through everyday as I do with my Hotmail E-mails and EETimes RSSs.

It's all about Timing：

Sun Nov 08 2009 09:35:01 GMT+0800 Timing Analysis of a Source Synchronous Interface Using ALTLVDS Thanks again! Kwalt.

Wed Nov 4 2009 21:01:49 UTC+0800 Slack:Not operational: Clock Skew>Data Delay ... No answers yet. Do an experiment myself.

Wed Nov 4 2009 20:46:41 UTC+0800 Timing constraints for ALTLVDS I/O 

Wed Nov 4 2009 20:44:29 UTC+0800 Constraining SOPC Builder designs using TimeQuest
Wed Nov 04 2009 00:26:23 GMT-0800 (Pacific Standard Time) Instantiate primitive DFF with an an inverted clock input "the inverter get absorbed into the LAB clock inversion and there is no clock skew and no timing issues"
Wed Nov 04 2009 00:12:59 GMT-0800 (Pacific Standard Time) Timing Analysis of Internally Generated Clocks in Timequest   kwalt, How many thanks I owe you!
Wed Nov 04 2009 00:11:35 GMT-0800 (Pacific Standard Time) The inconsistent results of the Timequest
Wed Nov 04 2009 00:08:23 GMT-0800 (Pacific Standard Time) How to Constraint Source-Synchronous Double-Data Rate Interfaces
Wed Nov 04 2009 00:07:33 GMT-0800 (Pacific Standard Time) Recovery timing errors using clock crossing bridge
Wed Nov 04 2009 00:04:29 GMT-0800 (Pacific Standard Time) set_clock_groups notes
Wed Nov 04 2009 00:02:47 GMT-0800 (Pacific Standard Time) case analysis and false path issues
Wed Nov 04 2009 00:00:51 GMT-0800 (Pacific Standard Time) Timequest: WHY? Pros and Cons!
Tue Nov 03 2009 23:40:59 GMT-0800 (Pacific Standard Time) Centering the Clock in the Data Valid Window for Source Syncrhonous Inputs
Tue Nov 03 2009 23:39:04 GMT-0800 (Pacific Standard Time) Timing Analysis of Source Synchronous Outputs
Tue Nov 03 2009 23:38:08 GMT-0800 (Pacific Standard Time) Implementing a Source Synchronous Interface between Altera FPGAs v2.0
Tue Nov 03 2009 23:24:57 GMT-0800 (Pacific Standard Time) Clock setup and hold slack explained
Tue Nov 03 2009 23:11:44 GMT-0800 (Pacific Standard Time) Applying multicycle assignments
Sun Nov 01 2009 17:17:32 GMT+0800 signal transfer in different clock domains
Sun Nov 01 2009 16:53:26 GMT+0800 Implementation and Timing of Reset Circuits
Sun Nov 01 2009 16:46:41 GMT+0800 Timequest & Output delay problem "I've found it easy to totally get wrapped up into equations and lost in the details."
Sun Nov 01 2009 16:39:19 GMT+0800 PLL Compensation warning Still not quite clear about this. Need to do a experiment myself.
Sun Nov 01 2009 16:37:35 GMT+0800 I need a low jitter clock mux in logic cells "We then use a phase-frequency detector to track the difference between the CRU clock and the reference clock. We can then tune our reference clock to match the frequency of the CRU clock." Have I missed out similar in-house designs?
Sun Nov 01 2009 16:36:16 GMT+0800 Understanding Recovery and Removal in TimeQuest Will study it carefully when I have time.
Sun Nov 01 2009 16:35:14 GMT+0800 Ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks This one really helps. It guided my recent work to a success!

On the Boundaries:

Wed Nov 04 2009 21:32:58 GMT+0800 are all GND pins connected internally to GND?

Wed Nov 4 2009 20:51:20 UTC+0800 SMII to MII converter ref design

Wed Nov 4 2009 20:48:46 UTC+0800 Stratix II DPA Reference design
Tue Nov 03 2009 23:47:52 GMT-0800 (Pacific Standard Time) CDR Data Non-Randomness Detection
Tue Nov 03 2009 23:32:33 GMT-0800 (Pacific Standard Time) Migrating Xilinx V2-Pro MGTs to Altera Stratix II GXBs
Sun Nov 01 2009 17:08:20 GMT+0800 how to sample io pin using signaltap 2 logic analyzer? Need to do some experiments myself.
Sun Nov 01 2009 17:06:40 GMT+0800 lvds simulation of stratix 4 using cst design studio Can anyone help him/her/me?
Sun Nov 01 2009 17:04:11 GMT+0800 What kind of pad does the Quartus select when I configure the i/o as single-ended
Sun Nov 01 2009 17:01:12 GMT+0800 Differential pair and Single-ended pins in HSMC of StratixIII 3SL150 kit
Sun Nov 01 2009 16:55:36 GMT+0800 how to connect PLL output to default pin What we can do or what we cannot do with the PLLs/Clkctrls are never clear until we reached the P&R stage. Isn't this inconvenient?

Call me a "Flow Guy":
Sun Nov 01 2009 17:15:04 GMT+0800 How to maximize license utilization? Help myself!
Sun Nov 01 2009 17:03:16 GMT+0800 log files generated by Quartus. Can anyone help him/her/me?
Sun Nov 01 2009 16:50:47 GMT+0800 Handling Quartus executable return codes I've long been planning on a blog post about how to control the compilation flow within Tcl.

Tricks:
Sun Nov 01 2009 17:21:42 GMT+0800 How to extract 1bit from a bus in a Block Diagram/Schematic File
Sun Nov 01 2009 17:12:13 GMT+0800 X_on_violation_option

IPs:

Wed Nov 4 2009 21:06:29 UTC+0800 programmable input output slave peripheral with programmable interrupts
Tue Nov 03 2009 23:42:14 GMT-0800 (Pacific Standard Time) Example of a PLL lock circuit using logic Interesting!
Tue Nov 03 2009 23:22:47 GMT-0800 (Pacific Standard Time) Synthesizing Equations What a gentleman!
Tue Nov 03 2009 23:04:02 GMT-0800 (Pacific Standard Time) Hardware version number
Tue Nov 03 2009 23:00:56 GMT-0800 (Pacific Standard Time) Avalon MM Master VHDL Templates
Tue Nov 03 2009 22:59:26 GMT-0800 (Pacific Standard Time) Avalon OpenCores 10/100 Ethernet MAC with InterNiche driver

Configuration:

Wed Nov 4 2009 20:58:50 UTC+0800 jtag player: eCos=>CyclII & epcs
Tue Nov 03 2009 23:45:48 GMT-0800 (Pacific Standard Time) Configuration estimator on Cyclone III
Tue Nov 03 2009 23:44:06 GMT-0800 (Pacific Standard Time) Programming EPCS devices with JTAG
Tue Nov 03 2009 23:33:19 GMT-0800 (Pacific Standard Time) Design example for Remote System upgrade
Tue Nov 03 2009 23:12:41 GMT-0800 (Pacific Standard Time) Fast Passive Parallel Configuration Controller Design

Simulation:

Wed Nov 4 2009 20:55:58 UTC+0800 Using hardware to accelerate simulation - ref design

Similar forums I cannot afford to miss:

AllInterview.com VLSI interview Q&As

EDAboard.com Somebody shows up here!

DeepChip.com ESNUGs = E-Mail Synopsys Users Group. Profile: John Cooley of ESNUG

DSP技术原理文章汇总

Mon Mar 01 2010 09:53:28 GMT+0800 (China Standard Time) 不断演变的数字信号处理技术

Mon Jul 27 2009 21:50:06 GMT-0700 (Pacific Daylight Time) Optimizing sort algorithms on DSPs

Mon Nov 10 2008 18:09:13 UTC+0800 Using object-oriented MATLAB for DSP

Mon Nov 10 2008 07:28:11 UTC+0800 The math of DSP, part 1: Series, integration, and frequency

Mon Nov 10 2008 07:26:49 UTC+0800 Desert Island Design: Bridging the (filter) gap without software

Mon Nov 10 2008 07:25:26 UTC+0800 Modular Arithmetic: A Divisive Issue

Sun Nov 9 2008 09:03:36 UTC+0800 Speeding up the CORDIC algorithm with a DSP

Wed Sep 17 2008 22:32:28 UTC+0800 Implementation of the AES algorithm on Deeply Pipelined DSP/RISC Processor

Mon Aug 25 2008 22:21:43 UTC+0800 Wireless data rates, part 1: Bandwidth, noise, and interference

Sun Aug 17 2008 14:17:06 UTC+0800 HDMI's Lip Sync and audio-video synchronization for broadcast and home video

Sat Jul 12 2008 16:47:25 UTC+0800 DSP Tricks: Computing Fast Fourier Transform Twiddle Factors

Sat Jun 14 2008 09:01:20 UTC+0800 Using the Decibel

Fri Jan 25 2008 15:38:25 UTC+0800 基于FPGA的分布式算法FIR滤波器设计

How to implement double-precision floating-point on FPGAs

Digital Signal Processing Tricks - Fast multiplication of complex numbers以上两篇文章内容很不错，在以后进行DSP设计时用得上。

How to map the H.264/AVC video standard onto an FPGA fabric

Generate FPGA designs from M-code这才是从算法到实现的全程解决方案。

Wavelet data hiding using Achterbahn-128 on FPGAs

计算机组成原理文章汇总

COMPILER & DEBUGGER TECHNOLOGY

Tue Mar 09 2010 09:19:48 GMT+0800 (China Standard Time) Decompiling the ARM architecture code

Tue Mar 09 2010 09:21:54 GMT+0800 (China Standard Time) Undo updates its Linux reversible debugger

RECONFIGURABLE COMPUTING

Thu Feb 25 2010 13:14:32 GMT+0800 (China Standard Time) Dodging Amdahl's Law with message passing, FPGA-based, parallel processing

Mon Jun 01 2009 02:14:17 GMT-0700 (Pacific Daylight Time) Processor startup claims 400 customers, fast growth

Thu Apr 23 2009 22:06:59 GMT-0700 (Pacific Daylight Time) ST rolls Morpheus reconfigurable processor

INTERCONNECT TECHNOLOGY

Mon Jan 04 2010 21:44:14 GMT-0800 (Pacific Standard Time) Understanding Factors Affecting Intel QuickPath Interconnect Signal Integrity

Sat Oct 17 2009 08:38:45 GMT+0800 Networks on a Chip Not Just Another NoC NoC Joke

Mon Jun 01 2009 02:19:30 GMT-0700 (Pacific Daylight Time) SOFTWARE TOOLS: Tundra releases its RapidIO System Modeling Tool

Mon Feb 23 2009 13:47:29 UTC+0800 How to pick a RapidIO switch

Tue May 05 2009 21:57:28 GMT-0700 (Pacific Daylight Time) Tools helps make on-chip interconnects

Mon Jul 27 2009 22:50:48 GMT-0700 (Pacific Daylight Time) Changing SoC design methodologies to automate IP integration and reuse

MULTICORE TECHNOLOGY

Tue Mar 09 2010 09:36:06 GMT+0800 (China Standard Time) Enhancing MCU performance with a DMA-based event system controller

Wed Mar 03 2010 10:25:33 GMT+0800 (China Standard Time) Threading the Needle Imagination Technology’s META Processor Gets Clever with Threads

Tue Jan 05 2010 17:18:04 GMT-0800 (Pacific Standard Time) Online forum focuses on multicore packet processing

Mon Oct 19 2009 19:54:57 GMT-0700 (Pacific Daylight Time) Using a scheduled cache model to reduce memory latencies in multicore DSP designs

Mon Jul 27 2009 22:48:57 GMT-0700 (Pacific Daylight Time) Virtual multi-core designs simplify real-time system design

Mon Jun 01 2009 02:11:07 GMT-0700 (Pacific Daylight Time) CPUs: HD1 app processor offers full HD video recording & playback

Mon May 04 2009 22:04:39 GMT-0700 (Pacific Daylight Time) Maximize multicore performance with content aware routing

Mon Feb 16 2009 18:06:02 UTC+0800 Programmable coprocessor generation from executable code

Mon Feb 16 2009 18:43:52 UTC+0800 PRODUCT FOCUS: The Value of Signal Processing in a Programmable Environment MathStar is still alive!?

Fri Jan 23 2009  11:20:07 UTC+0800 Analysis: Why massively parallel chip vendors failed 

Thu Jan 22 2009 18:11:14 UTC+0800 Massively parallel processors: Who's still alive?

Thu Dec 11 2008 13:07:48 GMT+0800 The Nulticore effect

Tue Nov 11 2008 06:47:06 UTC+0800 The network is the real-time processing system LARGE SCALE MULTICORE

Tue Nov 11 2008 06:44:58 UTC+0800 Got OCP? The Role of the OCP in Multicore Designs

Tue Nov 11 2008 06:42:18 UTC+0800 Plurality debuts new Hypercore development tools

Mon Nov 10 2008 18:29:57 UTC+0800 Arteris enhances its interconnect IP and toolset

Sun Nov 9 2008 08:58:59 UTC+0800 Multi-Core -- A New Challenge for Debugging

Sun Nov 9 2008 08:57:51 UTC+0800 Taking a closer look at Intel's Atom multicore

Sun Nov 9 2008 08:57:16 UTC+0800 Multicore SoCs change interconnect requirementsprocessor architecture

Sun Nov 9 2008 08:56:33 UTC+0800 20 years of switching fabric

Sun Nov 9 2008 08:56:07 UTC+0800 In multicore SOC architectures, buses are a last resort

半导体工艺文章汇总

Architecture

Tue Mar 02 2010 13:31:52 GMT+0800 (China Standard Time) Tabula tips time-share FPGA architecture

DFT

Sun Feb 21 2010 15:41:13 GMT+0800 (CST) Facilitating at-speed test at the register transfer level

Tue Jan 26 2010 21:02:18 GMT-0800 (Pacific Standard Time) Design for diagnosis to improve IC yield

Sun Dec 27 2009 22:10:52 GMT-0800 (Pacific Standard Time) In-design metal fill key to physical verification turnaround time for advanced IC designs

Sun Dec 27 2009 19:29:22 GMT-0800 (Pacific Standard Time) Bottlenecks removal in Design-For-Test flows for complex SoCs

Timing

Thu Feb 25 2010 13:23:49 GMT+0800 (China Standard Time) What if what-if analysis won't work at 28nm?

Sun Jan 17 2010 21:35:10 GMT-0800 (Pacific Standard Time) Timing Closure Methodology for Advanced FPGA Designs The Altera Timing Closure Methodology

Mon Jan 04 2010 21:42:46 GMT-0800 (Pacific Standard Time) How do you qualify netlist reduction and circuit extraction?

Sun Dec 27 2009 19:22:45 GMT-0800 (Pacific Standard Time) Synthesizing a New Category Oasys Turns Synthesis Upside Down

Wed Nov 18 2009 18:01:04 GMT-0800 (Pacific Standard Time) Taking Exception Verifying and Generating False and Multi-cycle Path Constraints

Wed Nov 11 2009 16:41:37 GMT-0800 (Pacific Standard Time) Optimize circuit designs with better crosstalk-aware routing techniques

Sun Nov 08 2009 23:47:53 GMT-0800 (Pacific Standard Time) Probabilistic Timing Analysis

Sun Nov 08 2009 23:47:11 GMT-0800 (Pacific Standard Time) Bridging SOC Architectures for Faster Timing Closure

Sun Nov 08 2009 23:46:27 GMT-0800 (Pacific Standard Time) Accelerate Design Closure with Multi-Core Timing Analysis and Optimization

Tue Nov 03 2009 22:11:48 GMT-0800 (Pacific Standard Time) 靜態時序分析（Static Timing Analysis）基礎及應用（下）

Tue Nov 03 2009 22:10:37 GMT-0800 (Pacific Standard Time) 靜態時序分析（Static Timing Analysis）基礎及應用（上）

Tue Nov 03 2009 22:07:42 GMT-0800 (Pacific Standard Time) Circuit Design Hint: Calculating Corner Independent Timing Closure

Thu Oct 29 2009 20:11:11 GMT+0800 Moving Data across Asynchronous Clock Boundaries

Wed Oct 28 2009 18:05:42 GMT-0700 (Pacific Daylight Time) Static Timing Analysis Increases ASIC Performance

Thu Oct 08 2009 10:36:48 GMT+0800 DIAGNOSING CDC ERRORS IN FPGAs

Thu Oct 01 2009 09:47:17 GMT+0800 Design Hint: Reduce the clock-tree power drag in your circuit implementation

Thu Oct 01 2009 07:28:51 GMT+0800 Don't Let Metastability Cause Problems in Your FPGA-Based Design

Wed Sep 09 2009 19:23:00 GMT-0700 (Pacific Daylight Time) IP Solutions for Synchronizing Signals that Cross Clock Domains Synopsys know-how revealed!

Wed Aug 26 2009 18:31:57 GMT-0700 (Pacific Daylight Time) 成功解决FPGA设计时序问题的三大要点

Sat Aug 29 2009 21:49:11 GMT+0800 Catching Mr. X: Diagnosing CDC Errors in FPGAs

Mon Aug 10 2009 22:44:08 GMT-0700 (Pacific Daylight Time) Verification and generation of constraints

Processing

Mon Feb 01 2010 23:42:51 GMT-0800 (Pacific Standard Time) ASIC pioneer reinvents 3-D FPGAs

Mon Dec 28 2009 00:44:11 GMT-0800 (Pacific Standard Time) DRAM: the field for material and process innovation

Sun Dec 27 2009 22:17:59 GMT-0800 (Pacific Standard Time) Easier cross-domain signal protection for mixed-signal SoCs

Mon Dec 21 2009 21:35:19 GMT-0800 (Pacific Standard Time) Making the shift from floating-gate to phase-change in non-volatile memory

Mon Oct 19 2009 20:01:29 GMT-0700 (Pacific Daylight Time) NAND Flash competition fueled by advanced lithography technology

Fri Oct 02 2009 12:19:53 GMT+0800 Researchers present MRAM-based FPGA architecture

Mon Mar 23 2009 22:02:01 GMT-0700 (Pacific Daylight Time) Process variability becoming competitive weapon?

Sun Dec 14 2008 20:56:05 UTC+0800 How to exploit the uniqueness of FPGA silicon for security applications

Thu Dec 11 2008 13:11:02 GMT+0800 China chips: Bomb, or just a lot of firecrackers?

Sat Sep 6 2008 09:25:47 UTC+0800 A Comprehensive Approach to Manufacturing Variability

Fri Sep 5 2008 12:45:58 UTC+0800 When the Walls Get Too Thin

Fri Sep 5 2008 12:42:05 UTC+0800 Apples to Apples

Fri Sep 5 2008 12:41:37 UTC+0800 The Big eASY

Fri Sep 5 2008 12:41:12 UTC+0800 How Many Nanometers Do I Need?

Fri Sep 5 2008 12:36:03 UTC+0800 Will memristors prove irresistible?

Fri Sep 5 2008 12:35:09 UTC+0800 When atoms count

Fri Sep 5 2008 12:34:48 UTC+0800 Reading the tea leaves

网络测试测量文章汇总

Sunrise Telecom in the News 

JDSU in the News

EXFO in the News

Ixia in the News

Tue Mar 02 2010 13:08:12 GMT+0800 (China Standard Time) PRODUCT HOW TO: Improving switch maintenance in PXI with BIRST

Thu Feb 25 2010 13:50:49 GMT+0800 (China Standard Time) Forget ICT--Use MDI Testing with 10GBASE-T PHY

Sun Feb 21 2010 13:49:50 GMT+0800 (CST) 40/100-Gigabit Ethernet: Watching the clock

Wed Feb 17 2010 15:21:07 GMT+0800 (CST) Achieve High Availability in VoIP: An Implementation Example--Part II

Wed Feb 17 2010 15:19:22 GMT+0800 (CST) Achieve High Availability in VoIP: An Implementation Example--Part I

Tue Feb 16 2010 07:51:46 GMT+0800 (CST) Backplane tutorial: RapidIO, PCIe and Ethernet

Wed Feb 03 2010 17:08:17 GMT-0800 (Pacific Standard Time) The basics of clock jitter in embedded system designs

Wed Feb 03 2010 17:07:34 GMT-0800 (Pacific Standard Time) Automating next generation network design tasks

Thu Jan 28 2010 21:03:53 GMT-0800 (Pacific Standard Time) Network engineering for audio engineers

Tue Jan 26 2010 23:10:06 GMT-0800 (Pacific Standard Time) PMC readies OTN linecard ICs As OTN spreads from the backbone to the access network, service providers and enterprises look to a new generation of line-card silicon.

Tue Jan 26 2010 21:16:55 GMT-0800 (Pacific Standard Time) IP networks’ spread brings challenges to networking SOCs A trend involving the seemingly complete victory of IP (Internet Protocol) over rival protocols and the concomitant spread of GbE (gigabit Ethernet) is drawing together disparate networks, vastly simplifying facilities management for network operators but creating a pain for silicon designers.

Tue Jan 26 2010 21:15:31 GMT-0800 (Pacific Standard Time) Congestion management clears a path through 10 GbE With the new IEEE standards for consolidation and the ability to build highly scalable high-speed Ethernet networks, Ethernet will become the only fabric you need for converged data centers, and it will lower the cost of supercomputer networks.

Tue Jan 26 2010 21:06:31 GMT-0800 (Pacific Standard Time) Using SerDes in Fourth Generation Wireless Infrastructure

Fri Jan 22 2010 01:17:51 GMT-0800 (Pacific Standard Time) 光通信未来发展的热点技术展望

Tue Jan 19 2010 21:14:52 GMT-0800 (Pacific Standard Time) CASE STUDY: Flying Safely with 10 Gigabit-Ethernet

Mon Dec 28 2009 00:42:24 GMT-0800 (Pacific Standard Time) Using IEEE-1588 transparent clocks to improve system time synchronization accuracy

Sun Dec 27 2009 22:21:20 GMT-0800 (Pacific Standard Time) Coordinated debugging of distributed systems

Sun Dec 27 2009 18:52:51 GMT-0800 (Pacific Standard Time) Telling Time Over Ethernet

Mon Dec 21 2009 22:13:10 GMT-0800 (Pacific Standard Time) How to provide Internet Video Quality of Experience

Mon Dec 21 2009 22:12:40 GMT-0800 (Pacific Standard Time) Building a network performance analysis test system with Linux, Tcl/TK, SQL & extremeDB

Tue Nov 17 2009 20:18:24 GMT-0800 (Pacific Standard Time) PRODUCT HOW-TO: Dial tone detector based on monobit periodograms

Mon Nov 16 2009 21:01:41 GMT-0800 (Pacific Standard Time) Picking the right technologies for your home network design

Tue Nov 03 2009 22:01:22 GMT-0800 (Pacific Standard Time) PRODUCT HOW-TO: Removing deterministic jitter & interference due to noisy power supplies

Wed Oct 28 2009 18:21:12 GMT-0700 (Pacific Daylight Time) Ensuring the success of High Speed Ethernet (HSE)

Thu Oct 01 2009 09:30:32 GMT+0800 Implementing cost-effective gigabit serial links over cable

Thu Oct 01 2009 08:17:46 GMT+0800 Arasan adds IEEE 1588 PTP support to Ethernet IP Core

Thu Oct 01 2009 08:08:41 GMT+0800 Symmetricom Announces IEEE 1588 PTP v2 Grandmaster Clock For Precise Time And Frequency Measurement Over Ethernet

Thu Oct 01 2009 07:15:13 GMT+0800 Solarflare integrates 10GBase-T on a single chip

Wed Sep 30 2009 21:38:20 GMT+0800 Data buffering with FPGAs in a disproportional line rate environment

Mon Sep 28 2009 22:20:53 GMT-0700 (Pacific Daylight Time) Multicores can transform IP-based wired/wireless networking Multicores can transform IP-based wired/wireless networking

Thu Sep 24 2009 20:19:58 GMT-0700 (Pacific Daylight Time) Power over Ethernet (PoE) grows up: it's now PoE+

Thu Sep 24 2009 19:57:07 GMT-0700 (Pacific Daylight Time) Fast Channels Make Light Work

Sun Sep 20 2009 22:02:48 GMT-0700 (Pacific Daylight Time) Gaming the system--high-end networking on the Cell processor

Sat Aug 29 2009 21:17:09 GMT+0800 Taming a Tenth of a Terabit FPGAs in 100GbE Tester

Thu Aug 20 2009 22:10:58 GMT-0700 (Pacific Daylight Time) How to achieve multi-dwelling unit access to passive optical networks

Thu Aug 06 2009 22:21:14 GMT-0700 (Pacific Daylight Time) JDSU to acquire Network Tools Business from Finisar

Mon Jul 27 2009 22:00:57 GMT-0700 (Pacific Daylight Time) Understanding Service Availability--An Industry in Transition

Tue Jul 07 2009 20:48:08 GMT-0700 (Pacific Daylight Time) A Measure of Respect

Thu Jun 18 2009 21:42:34 GMT-0700 (Pacific Daylight Time) U.S. readies broadband stimulus details

Mon Jun 01 2009 02:32:31 GMT-0700 (Pacific Daylight Time) Design Tip: Simulating "Raw" Error Vector Magnitude (EVM) for a Quick Measure of a Circuit's EVM Performance

Sun May 31 2009 21:44:13 GMT-0700 (Pacific Daylight Time) Spirent renames its Best in Test-winning protocol-analysis module

Mon May 11 2009 22:10:53 GMT-0700 (Pacific Daylight Time) Understanding IEEE's new audio video bridging standards

Tue May 05 2009 22:03:19 GMT-0700 (Pacific Daylight Time) Combine Power over Ethernet & Power Line Carrier for low cost & low power networking

Tue May 05 2009 22:02:45 GMT-0700 (Pacific Daylight Time) Take advantage of powerline communications in nextgen home networking & IPTV designs

Mon May 04 2009 21:55:02 GMT-0700 (Pacific Daylight Time) 1394 Automotive network enables powerful, cost-efficient in-vehicle networks for infotainment, navigation, cameras

Tue Apr 28 2009 21:35:59 GMT-0700 (Pacific Daylight Time) White Paper :: The Field Engineer’s Challenge - from LAN to Carrier Ethernet

Tue Apr 28 2009 21:35:23 GMT-0700 (Pacific Daylight Time) It's the network, really

Thu Apr 23 2009 22:12:57 GMT-0700 (Pacific Daylight Time) In-vehicle communications — is fibre optic cable set to replace copper?

Thu Apr 02 2009 21:43:14 GMT-0700 (Pacific Daylight Time) BT Selects Fanfare As Key Component Of Its Strategic Platform For Automating Network Testing

Sun Mar 29 2009 22:07:28 GMT-0700 (Pacific Daylight Time) Innovations keep coming at OFCNFOEC 2009

Sun Mar 29 2009 22:06:47 GMT-0700 (Pacific Daylight Time) 40G and 100G Ethernet: The hype has arrived

Wed Mar 25 2009 22:30:08 GMT-0700 (Pacific Daylight Time) Digital Lightwave Announces Battery Powered 40G Test Set

Wed Mar 25 2009 22:14:32 GMT-0700 (Pacific Daylight Time) Fanfare teams with Agilent to automate network testing
Mon Mar 16 2009 22:37:04 PDT EXFO Launches Industry's Fastest Optical Sampling Oscilloscopes

Wed Mar 11 2009 22:52:52 PDT Who doesn't need Ethernet timestamps?

Wed Mar 11 2009 22:52:12 PDT An introduction to Synchronized Ethernet

Sun Mar 1 2009 21:56:23 UTC+0800 Home networking groups edge toward G.hn

Sun Mar 1 2009 21:55:24 UTC+0800 40-Gbps and 100-Gbps Ethernet will bring new test challenges

Sun Mar 1 2009 21:54:47 UTC+0800 40-Gbps and 100-Gbps Ethernet coming into focus

Sun Mar 1 2009 21:54:18 UTC+0800 When time and frequency matter

Mon Feb 23 2009  13:53:29 UTC+0800 Modules test network layers

Mon Feb 23 2009 13:52:02 UTC+0800 IP video surveillance standards

Mon Feb 23 2009 13:51:14 UTC+0800 Keeping Track of the Bandwidth Explosion in Aggregated Video

Mon Feb 23 2009 13:50:41 UTC+0800 Managing QoS for video delivery in shared-I/O environments

Wed Feb 4 2009 16:15:59 UTC+0800 Fluke Networks Introduces New MetroScope-LT Carrier Ethernet Analyzer To Meet Growth In Carrier Ethernet Deployment And Testing

Wed Feb 4 2009 16:15:24 UTC+0800 JDSU Adds AMCC EFEC Option To TestPoint 10Gbps Test Solution

Wed Feb 4 2009 16:14:37 UTC+0800 BERTScope: First BER-Based Jitter Decomposition Including Jitter Separation On PRBS-31 And PRBS-23 For Compliance To 8 GT/s PCI Express 3.0 And DisplayPort 5.4 Gb/s

Wed Feb 4 2009 16:14:02 UTC+0800 Frame Communications Lowers The Cost Of 10G Metro Ethernet Testing

Wed Feb 4 2009 16:13:31 UTC+0800 PCIe jammer provides inline-error injection

Wed Feb 4 2009 15:34:14 UTC+0800 Programmable logic innovation is overdue

Wed Jan 28 2009 14:27:46 UTC+0800 Commex 10GbE NIC enables multiple processing cores to be content aware

Fri Jan 23 2009 11:18:21 UTC+0800 JDSU adds triple-play tester to handheld portfolio

Fri Jan 23 2009 11:16:58 UTC+0800 EXFO unveils distributed PMD analyzer

Fri Jan 23 2009 11:15:33 UTC+0800 Anritsu handheld unit tests P25 communications systems

Fri Jan 23 2009 11:13:43 UTC+0800 COMMENTARY: The power of broadband over powerline

Thu Jan 22 2009 18:22:13 UTC+0800 What Every RF Engineer Should Know: Scopes

Thu Jan 22 2009 18:21:32 UTC+0800 Flexible, programmable 40 Gbps SerDes framer interface IP core

Thu Jan 22 2009 18:20:50 UTC+0800 LTE base station simulator evaluates next-gen LTE chipset and mobile device performance

Wed Jan 7 2009 13:46:55 UTC+0800 PRODUCT HOW-TO: Deploy hybrid Ethernet networks with a plesiocronous digital hierarchy

Wed Jan 7 2009 13:25:53 UTC+0800 GAO Provides Low Cost ADSL Tester

Wed Jan 7 2009 13:15:15 UTC+0800 Agilent Technologies, Astek Deliver Industry-First HyperTransport 3 Test Solution

Wed Jan 7 2009 13:14:47 UTC+0800 GL Communications enhances T1 E1 product lineup

Wed Jan 7 2009 13:11:37 UTC+0800 6-GHz SERDES chip charts its own eye diagram

Thu Dec 25 2008 13:53:07 UTC+0800 Designing protective circuitry for DSL loops: Beware of pitfalls

Thu Dec 25 2008 13:51:10 UTC+0800 Sunrise Telecom Sets Standard For Comprehensive DOCSIS And Euro DOCSIS 2.0 For Next-Generation Networks

Thu Dec 25 2008 13:50:25 UTC+0800 GAO Tek Announces ADSL Tester For xDSL Applications

Thu Dec 25 2008 13:49:53 UTC+0800 EXFO multiservice modules perform multistream testing

Thu Dec 25 2008 13:49:16 UTC+0800 EXFO's Ethernet test portfolio gains IPv6 support

Thu Dec 25 2008 13:48:48 UTC+0800 JDSU's handheld tester checks E1 and datacom circuits

Mon Dec 22 2008 18:36:15 UTC+0800 No operating system is an island

Sat Dec 20 2008 18:15:17 UTC+0800 Bell Labs puts 100 Gbps Ethernet to the test Demonstrates 100 Gbps transmission with Verizon and Deutsche Telekom

Mon Dec 15 2008 11:55:07 UTC+0800 40/100GE和10G高速以太网测试技术

Mon Dec 8 2008 12:52:51 UTC+0800 Intro to VoIP quality measurements

Fri Dec 5 2008 15:55:08 UTC+0800 Achieve higher accuracy using mixed-signal FPGA calibration

Wed Dec 3 2008 18:05:03 UTC+0800 EXFO Adds IPv6 Support To Its Ethernet Test Portfolio

Wed Dec 3 2008 18:04:36 UTC+0800 MRV's system automates 8-Gbps Fibre Channel test

Mon Dec 1 2008 13:04:33 UTC+0800 Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs

Sun Nov 30 2008 09:35:44 UTC+0800 MorethanIP Releases Complete SPAUI and RXAUI Solution for FPGAs and ASICs

Sun Nov 30 2008 09:22:37 UTC+0800 Telecom's Need for Speed

Fri Oct 3 2008 23:20:12 UTC+0800 Ixia Demonstrates Industry-First 40 Gigabit Ethernet Testing Capability

Fri Oct 3 2008 23:19:27 UTC+0800 EXFO software examines 40G network operation

Fri Oct 3 2008 23:12:09 UTC+0800 Demand grows for multiple-services testing

Fri Oct 3 2008 23:11:13 UTC+0800 Cooperation to compliance with SFP+

Mon Sep 8 2008 12:24:34 UTC+0800 EXFO unveils multiservice tester for Ethernet, Fibre Channel

Tue Aug 26 2008 20:18:00 UTC+0800 Agilent to present webinar on Logic Analyzer Basics

Mon Aug 25 2008 21:43:42 UTC+0800 Dynamic range unraveled

Mon Aug 25 2008 21:46:06 UTC+0800 Realize High Port Density 10GbE Networks

Mon Aug 25 2008 22:00:45 UTC+0800 MRV Announces All Optical 100 Gbps Cross Connect For Test Lab Automation

Mon Aug 25 2008 21:59:42 UTC+0800 NetQuest Launches First 10 Gigabit Test And Monitoring Access Solution To Optimize Tool Port Usage For Service Providers

Mon Aug 25 2008 21:59:00 UTC+0800 EXFO platform performs Web-based fiber plant monitoring

Mon Aug 25 2008 21:58:22 UTC+0800 Ixia and Fanfare form partnership to advance test automation

Mon Aug 25 2008 21:57:45 UTC+0800 JDSU extends capabilities of handheld 10-GigE field tester

Mon Aug 25 2008 21:57:12 UTC+0800 Anritsu enhances analyzer with traffic impairment emulation

Mon Aug 25 2008 21:56:19 UTC+0800 Trend's field tool tests carrier Ethernet networks

Thu Aug 14 2008 22:54:56 UTC+0800 How we froze our Software!

Tue Aug 12 2008 06:53:55 UTC+0800 How to implement a digital oscilloscope in Structured ASIC fabric 这篇文章也可以归类为“行业趋势”。

Thu Jul 24 2008 20:34:22 UTC+0800 Oscilloscopes harness quad-core CPUs, four-lane PCIe datapaths for 20-fold speed boost State of the art of Osilloscopes.

Thu Jul 24 2008 20:28:14 UTC+0800 Ixia CEO Atul Bhatnagar: Calm in the Storm...

Sat Jul 12 2008 16:35:08 UTC+0800 软件测试的基本原则

Sat Jul 12 2008 16:34:38 UTC+0800 软件测试中存在的问题

Sat Jul 12 2008 16:49:27 UTC+0800 PRODUCT HOW-TO: Achieving high quality HD video delivery over home networks

Sat Jul 12 2008 16:21:37 UTC+0800 The design-and-test merger

Sat Jul 12 2008 16:20:53 UTC+0800 Theory of relativity visits “real-time” clock

Sat Jul 12 2008 16:19:34 UTC+0800 From design to production An exclusive interview with a test engineer

Sun Jun 29 2008 20:10:45 UTC+0800 Protocol stack testing for LTE

存储技术文章汇总

Micron's Advanced Storage Blog

Denali Memory Report
 

Mon Mar 01 2010 09:52:33 GMT+0800 (China Standard Time) 面向纳电子时代的非易失性存储器

Mon Mar 01 2010 09:52:06 GMT+0800 (China Standard Time) 从磁性技术到固态非旋转技术：漫长奇特的存储技术演变历程

Thu Feb 25 2010 13:24:54 GMT+0800 (China Standard Time) Using FPGAs to build battery-free RAID cache memory systems

Tue Feb 16 2010 07:33:11 GMT+0800 (CST) Analysis: Why did Micron buy Numonyx?

Sun Feb 07 2010 23:42:37 GMT-0800 (Pacific Standard Time) Remembering the memories

Wed Feb 03 2010 18:36:53 GMT-0800 (Pacific Standard Time) Comment: Will 2010 see SSD technology topping out?

Tue Jan 26 2010 21:24:15 GMT-0800 (Pacific Standard Time) NAS reference design AppliedMicro Advanced NAS reference design features Power Architecture processing, comprehensive, hardware-software platform,industry-leading performance and advanced system design to embedded developers

Sun Jan 24 2010 21:31:33 GMT-0800 (Pacific Standard Time) Three-bit-per-cell NAND products entering main stage

Sun Dec 27 2009 22:16:10 GMT-0800 (Pacific Standard Time) Expanding the use of nonvolatile memory in data logging apps

Sun Dec 27 2009 22:14:53 GMT-0800 (Pacific Standard Time) Why PCIe-Based Systems Need Multicast

Sun Dec 27 2009 19:37:56 GMT-0800 (Pacific Standard Time) A mixed signal approach to debugging DDR DRAM interfaces

Sun Dec 27 2009 19:31:13 GMT-0800 (Pacific Standard Time) Designing Serial ATA IP into your embedded storage device design

Sun Dec 27 2009 19:30:28 GMT-0800 (Pacific Standard Time) Serial attached SCSI 2.0 IP solution targets embedded storage applications

Tue Nov 10 2009 20:09:14 GMT-0800 (Pacific Standard Time) Nonvolatile-logic route to instant-on With a little help from Nonvolatile momery, the PC can go into sleep in no time and wake up with instant-on speed. What a dream becomes true!!!

Tue Nov 10 2009 20:08:16 GMT-0800 (Pacific Standard Time) Universal memory, round two

Sun Sep 20 2009 21:49:02 GMT-0700 (Pacific Daylight Time) Minimizing latency in diverse embedded system design environments

Thu Aug 20 2009 00:31:35 GMT-0700 (Pacific Daylight Time) Sun scolds NAND makers, slams SSDs

Wed Aug 12 2009 22:22:24 GMT-0700 (Pacific Daylight Time) A new approach to ensuring file system integrity in mission-critical embedded systems

Wed Aug 12 2009 22:21:33 GMT-0700 (Pacific Daylight Time) Tutorial: the new JEDEC interface standard for data converters

Wed Jul 01 2009 18:55:06 GMT-0700 (Pacific Daylight Time) ONFI Introduces 2.1 Specification, Sets New Speed Record

Wed Jul 01 2009 18:29:53 GMT-0700 (Pacific Daylight Time) Micron Introduces New 34-Nanometer High-Density NAND Products, Increasing Performance and Reducing Die Size

Tue Jun 30 2009 21:44:35 GMT-0700 (Pacific Daylight Time) Taking the West Bridge to higher mass storage densities on Digital Still Cameras

Tue Jun 16 2009 22:16:03 GMT-0700 (Pacific Daylight Time) Serial Attached SCSI storage moves ahead in network server designs

Mon Jun 15 2009 22:00:25 GMT-0700 (Pacific Daylight Time) 固态硬盘2012年将成第三大闪存产品

Tue Jun 09 2009 21:58:27 GMT-0700 (Pacific Daylight Time) I/O Virtualization (IOV) & its uses in the network infrastructure

Mon Jun 01 2009 02:07:54 GMT-0700 (Pacific Daylight Time) Using multi-root (MR) PCIe to extend nextgen multi-host storage & server switch fabrics

Sun May 31 2009 21:46:29 GMT-0700 (Pacific Daylight Time) Maximizing Flash Lifetimes

Tue May 05 2009 21:59:18 GMT-0700 (Pacific Daylight Time) PCI expansion card promises complete solid state storage system

Sat Mar 28 2009 22:11:35 GMT+0800 集成电路设计中心“IDE加解密专用芯片产业化”项目成功验收

Wed Mar 18 2009 22:21:13 GMT-0700 (Pacific Daylight Time) LSI推MegaRAID软件 增强固态硬盘管理

Wed Mar 18 2009 22:16:39 GMT-0700 (Pacific Daylight Time) Fusion-io发布1.28TB版本超高速SSD

Wed Mar 18 2009 22:11:47 GMT-0700 (Pacific Daylight Time) 计世独家：固态硬盘将取代传统硬盘？

Tue Dec 23 2008 18:02:36 UTC+0800 NAND闪存：寿命问题终成桎梏？

Mon Dec 22 2008 13:14:42 UTC+0800 Micron, Sun take NAND endurance to one million cycles

Wed Dec 10 2008 13:36:36 UTC+0800 Quantum network storage problem overcome

Mon Dec 8 2008 13:02:56 UTC+0800 Take advantage of system performance with higher-density SRAMs

Mon Dec 8 2008 13:02:33 UTC+0800 Using nvSRAMS to supercharge flash memory devices in data-logging applications

Sun Sep 7 2008 21:00:42 UTC+0800 StorageMojo

Sun Sep 7 2008 21:00:18 UTC+0800 Enterprise SSDs

Sun Sep 7 2008 20:59:45 UTC+0800 Withdrawals and my addiction to speed

Sat Sep 6 2008 17:49:18 UTC+0800 拆除硬盘 百度服务器改用闪存

Sat Sep 6 2008 17:47:10 UTC+0800 英特尔发布新款固态硬盘 读取速度达240MB/ｓ

Wed Sep 3 2008 23:14:42 UTC+0800 Flash Flood - We Never Thought...

Wed Sep 3 2008 12:03:46 UTC+0800 英特尔发布高性能SATA固态驱动器产品规划

Tue Aug 19 2008 12:55:19 UTC+0800 Three options for designing NAND flash memory subsystems

Tue Aug 12 2008 06:39:05 UTC+0800 AMCC, Hifn team to create networking, storage reference designs

Thu Jul 24 2008 20:36:11 UTC+0800 Spansion, Virident aim to slash power in server farms “大”内存，冷内存。

Sat Jul 12 2008 16:40:43 UTC+0800 Hard disk vs. Flash video storage: Hybrid technology merges best of each

Sat Jun 21 2008 10:14:27 UTC+0800 Recent Advances in WAN Acceleration Technologies 用类似于CVS使用的“增量备份”的方法传输差异数据，用“传输符号”代替传输重复数据，同时增大TCP的传输窗口。Client/Server和本地的WAN加速设备之间传递全部数据，WAN加速设备对用户请求进行分析和归类。在WAN两端分别有一台这样的设备，两台设备之间只传递“差异数据”和“符号”。对数据进行分析和归类的算法很重要。WAN两端的设备最初的数据同步不可避免地要传输全部重复数据，而且对于“重复数据”的定义还要有一个学习或协商过程。

Wed Mar 25 2009 01:45:14 GMT-0700 (Pacific Daylight Time) 一种绑定计算资源和存储资源的装置

Tue Sep 2 2008 22:54:30 UTC+0800 一种绑定计算资源和存储资源的装置

Tue Sep 2 2008 22:45:35 UTC+0800 数据缓存装置和采用该装置的网络存储系统及缓存方法

Tue Sep 2 2008 22:46:16 UTC+0800 本地存储协议接口和网络存储协议接口间的数据传输方法

开发方法学文章汇总

Tue Mar 09 2010 09:25:12 GMT+0800 (China Standard Time) Getting disciplined about embedded software development

Thu Mar 04 2010 12:10:18 GMT+0800 (China Standard Time) Paved with Good Intentions Replacing Judgement with Process IS a "Scenic Walk to HELL", although it is paved with good intentions.

Tue Mar 02 2010 13:20:29 GMT+0800 (China Standard Time) Time to market is a critical consideration Being first is key, unless you can be substantially better. Being third means being out of luck.

Tue Mar 02 2010 13:13:30 GMT+0800 (China Standard Time) Incorporating quality into reusable IP

Thu Feb 25 2010 13:59:45 GMT+0800 (China Standard Time) Executing software contracts

Wed Feb 03 2010 18:39:58 GMT-0800 (Pacific Standard Time) Lifecycle development comes to complex critical software projects

Wed Feb 03 2010 18:39:18 GMT-0800 (Pacific Standard Time) When good compilers go bad, or What you see is not what you execute

Thu Jan 28 2010 21:02:49 GMT-0800 (Pacific Standard Time) Analysis tool eases reuse of legacy code

Tue Jan 26 2010 21:04:51 GMT-0800 (Pacific Standard Time) A nuts and bolts engineering approach to using open source IP

Tue Jan 19 2010 21:14:06 GMT-0800 (Pacific Standard Time) Defense in depth: Reducing embedded software bugs using static analysis and coding rules

Fri Jan 08 2010 01:54:05 GMT-0800 (Pacific Standard Time) Make legal compliance an integral part of the software quality assurance process

Sun Dec 27 2009 19:35:04 GMT-0800 (Pacific Standard Time) Why standards still matter Demystifying the standards development process

Mon Dec 28 2009 00:29:22 GMT-0800 (Pacific Standard Time) COMMENTARY: How to bring out the best in your design team

Sun Dec 27 2009 22:20:19 GMT-0800 (Pacific Standard Time) Viewpoint: How to bring out the best in your design team

Sun Dec 27 2009 22:08:45 GMT-0800 (Pacific Standard Time) Why, When and How: The basics of embedded systems prototyping

Sun Dec 27 2009 18:14:14 GMT-0800 (Pacific Standard Time) How to use a debugger as a bug preventive tool

Wed Dec 23 2009 19:06:28 GMT-0800 (Pacific Standard Time) How to travel safely in embedded code space

Wed Dec 23 2009 18:27:52 GMT-0800 (Pacific Standard Time) Legal compliance and open source software

Wed Dec 02 2009 16:33:51 GMT-0800 (Pacific Standard Time) Multisite, collaborative hardware design calls for HCM

Mon Nov 16 2009 21:30:30 GMT-0800 (Pacific Standard Time) Use formal, online communication to deliver design quality closure

Wed Nov 04 2009 18:10:46 GMT-0800 (Pacific Standard Time) Going For Golden Tracing Requirements with LDRA’s TBreq

Thu Oct 01 2009 07:31:21 GMT+0800 FPGA outsourcing: Ten questions you should ask

Mon Sep 28 2009 22:29:24 GMT-0700 (Pacific Daylight Time) Reducing costs with embedded software optimization

Mon Sep 28 2009 22:27:57 GMT-0700 (Pacific Daylight Time) Developing a good bedside manner

Mon Sep 28 2009 22:16:23 GMT-0700 (Pacific Daylight Time) Firmware architecture in five easy steps

Thu Aug 20 2009 22:09:41 GMT-0700 (Pacific Daylight Time) State charts can provide you with software quality insurance

Wed Aug 12 2009 22:16:01 GMT-0700 (Pacific Daylight Time) The best coding standards eliminate bugs

Wed Aug 12 2009 22:13:34 GMT-0700 (Pacific Daylight Time) As design goes global, tools get more critical

Wed Aug 12 2009 22:12:55 GMT-0700 (Pacific Daylight Time) Combining error-detection techniques to find bugs in embedded C software

Wed Aug 12 2009 22:12:01 GMT-0700 (Pacific Daylight Time) Measuring Changes in Software with CLOC

Mon Jul 27 2009 22:57:21 GMT-0700 (Pacific Daylight Time) Building a software test and regression plan

Mon Jul 27 2009 22:54:49 GMT-0700 (Pacific Daylight Time) Software Component Testing and Test Automation in Embedded Systems

Thu Jun 18 2009 21:43:19 GMT-0700 (Pacific Daylight Time) Ten essential elements to guarantee enhanced software quality

Sun Apr 19 2009 22:20:21 GMT-0700 (Pacific Daylight Time) What you need to know about automated testing and simulation

Mon May 04 2009 21:57:58 GMT-0700 (Pacific Daylight Time) Software Engineering versus "real" engineering

Mon May 04 2009 21:57:34 GMT-0700 (Pacific Daylight Time) Ensuring software quality & reliability with configuration & change management

Mon May 04 2009 21:56:56 GMT-0700 (Pacific Daylight Time) Requirements Management Reduces Software Defects and Improves Code Quality

Mon May 04 2009 21:56:08 GMT-0700 (Pacific Daylight Time) More bug-killing standards for firmware coding

Tue Apr 21 2009 22:16:00 GMT-0700 (Pacific Daylight Time) But What Does It Mean? Tagging, Indexing, and Querying Behaviors in RTL Designs

Tue Apr 14 2009 12:46:36 GMT+0800 (China Standard Time) Firmware Metrics

Sun Mar 29 2009 22:08:54 GMT-0700 (Pacific Daylight Time) Mean time between failure made easy

Thu Mar 26 2009 22:04:19 GMT-0700 (Pacific Daylight Time) Bug-killing standards for firmware coding

Wed Mar 25 2009 22:04:00 GMT-0700 (Pacific Daylight Time) Using software verification techniques in non-safety critical embedded software designs

Wed Mar 25 2009 22:02:53 GMT-0700 (Pacific Daylight Time) Virtualization makes better use of open-source OSes and apps

Mon Mar 23 2009 22:03:04 GMT-0700 (Pacific Daylight Time) Managing open-source software during system design

Wed Mar 11 2009 22:56:06 PDT A crash course in UML state machines

Wed Mar 11 2009 22:55:45 PDT Achieving Six Sigma Quality for IC Design

Sun Mar 1 2009 22:07:58 UTC+0800 More to IP reuse than software tweaks

Mon Feb 16 2009 18:03:53 UTC+0800 FPGA outsourcing: Ten questions you should ask

Fri Jan 23 2009 11:09:12 UTC+0800 The Truth Behind Static Analysis Pitfalls

Thu Jan 22 2009 18:19:17 UTC+0800 Static analysis tip: How to resolve statically detected defects

Thu Jan 22 2009 18:18:52 UTC+0800 Static analysis tip: How to Effectively Apply a Static Analysis Tool

Tue Jan 20 2009 15:27:57 UTC+0800 Mechanical vs. digital: a GUI isn't always the answer

Tue Jan 20 2009 15:26:59 UTC+0800 Paying attention to your software processes to achieve higher quality code

Wed Jan 7 2009 13:45:29 UTC+0800 Standardizing data interchanges among design tools in the ECU development process

Wed Jan 7 2009 13:42:39 UTC+0800 Skip bugging to speed delivery

Tue Dec 23 2008 18:03:55 UTC+0800 Planning, adopting and implementing adaptive reuse

Sun Dec 14 2008 21:13:01 UTC+0800 Use product line engineering to reduce the total costs required to create, deploy & maintain software code

Thu Dec 11 2008 13:20:40 UTC+0800 10 tips for writing more maintainable embedded software code

Thu Dec 11 2008 13:16:58 UTC+0800 Why Developers Need to Test - and How They Can Do It Better

Tue Dec 2 2008 22:21:41 UTC+0800 Lean coding

Sun Nov 30 2008 09:44:42 UTC+0800 Minimizing the Pain of RTL Design Reviews

Wed Sep 3 2008 23:25:17 UTC+0800 Modelling: not just for big boys?

Wed Sep 3 2008 23:06:12 UTC+0800 Does Harry Use Tools?

Wed Sep 3 2008 21:21:31 UTC+0800 Buzzword Bob - Taming the Team Tyrant

Fri Aug 29 2008 12:28:06 UTC+0800 Is there a specification for writing specifications?

Tue Aug 5 2008 21:55:40 UTC+0800 Building an FPGA Design Repository The tools are for free!

Sat Jul 12 2008 16:28:20 UTC+0800 Is your company looking for a world-leading program/project manager?

Fri Jul 11 2008 13:13:09 UTC+0800 Build checklists for embedded software projects

Sat Jun 14 2008 08:31:34 UTC+0800 Faster! Can we design embedded systems faster, cheaper, better?

Only Code Has Value? WHY is more important than WHAT in a document.

Do engineers really do R&D?预研项目和工程项目确实有很大的差异。制定时间表是立项的重要内容。制定得准确与否，是立项工作质量的判断标准。“小步快跑”，滚动式开发是个不错的方式。

Mon Jan 7 2008 11:01:54 UTC+0800 Get research out of development上一篇文章的系列二

Software Configuration Management Best Practices for Continuous Integration

Is Your SCM Tool Ready for Agile?

Using UML and SDL for Next Generation Networking (NGN)

Sun Jun 29 2008 21:26:52 UTC+0800 Keep your documentation close

职业体会文章汇总

FPGA技术实践文章汇总

实践性的：可以直接指导实践的，可以改进工作方法的。

Thu Feb 25 2010 14:08:37 GMT+0800 (China Standard Time) Partitioning an ASIC design into multiple FPGAs

Thu Feb 25 2010 14:05:11 GMT+0800 (China Standard Time) Leveraging FPGA and CPLD digital logic to implement analog to digital converters

Sun Feb 21 2010 16:24:02 GMT+0800 (CST) Chip synthesis: A new approach to RTL implementation

Sun Feb 21 2010 16:08:28 GMT+0800 (CST) Reusable VHDL IP in the real world

Tue Feb 16 2010 07:53:40 GMT+0800 (CST) Partitioning an ASIC Design into Multiple FPGAs

Thu Feb 25 2010 14:02:47 GMT+0800 (China Standard Time) Eeeeek! My FPGA's not working: Problems with the *IP*

Wed Feb 03 2010 18:41:13 GMT-0800 (Pacific Standard Time) Arrgghh! My FPGA's not working: Problems with the RTL

Tue Jan 19 2010 21:10:17 GMT-0800 (Pacific Standard Time) PRODUCT HOW-TO: Automating the FPGA Design Debug Process

Sun Jan 17 2010 21:23:02 GMT-0800 (Pacific Standard Time) Using an FPGA to tame the power beast in consumer handheld MPUs

Fri Jan 08 2010 01:46:37 GMT-0800 (Pacific Standard Time) Power Supply Design Considerations for Modern FPGAs

Mon Dec 28 2009 00:26:51 GMT-0800 (Pacific Standard Time) PRODUCT HOW-TO: Prototyping ASICs using FPGAs

Sun Dec 27 2009 18:54:43 GMT-0800 (Pacific Standard Time) Using yesterday's methodologies to design today's multi-FPGA systems is a recipe for disaster

Mon Nov 16 2009 21:43:10 GMT-0800 (Pacific Standard Time) Free JTAG tools provide new approach to board debugging

Mon Nov 16 2009 21:34:58 GMT-0800 (Pacific Standard Time) Boundary scan and JTAG emulation combine for advanced structural test and diagnostics

Tue Nov 03 2009 21:49:44 GMT-0800 (Pacific Standard Time) I/O Design Flexibility with the FPGA Mezzanine Card

Sun Oct 18 2009 21:57:46 GMT-0700 (Pacific Daylight Time) Lattice, Epson Toyocom offer differential reference clock solution

Thu Oct 08 2009 23:33:52 GMT-0700 (Pacific Daylight Time) Designing an accessible board

Thu Oct 08 2009 11:19:22 GMT+0800 Building a standard micro architecture

Thu Oct 08 2009 11:17:43 GMT+0800 FPGA Device Reliability and the Sunspot Cycle

Thu Oct 08 2009 11:16:07 GMT+0800 A technique for multi-line addressing in OLED displays

Thu Oct 08 2009 11:14:47 GMT+0800 Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems

Thu Oct 01 2009 07:27:58 GMT+0800 Using complex triggers in an FPGA-based RTL debugger

Mon Sep 28 2009 22:26:08 GMT-0700 (Pacific Daylight Time) Back to the basics: Doing Hardware Counter/Timer design using High School Science

Thu Sep 24 2009 20:16:38 GMT-0700 (Pacific Daylight Time) PRODUCT HOW-TO - Building high-speed FPGA memory interfaces

Sun Sep 20 2009 21:58:59 GMT-0700 (Pacific Daylight Time) JTAG test routines harness device functionality

Sun Sep 20 2009 21:52:36 GMT-0700 (Pacific Daylight Time) Control issues: How FPGAs can address MCUs' general-purpose I/O scaling wall

Wed Sep 09 2009 19:25:46 GMT-0700 (Pacific Daylight Time) Rethinking Reuse FPGA reuse is the same as PCB reuse.

Wed Aug 12 2009 22:18:12 GMT-0700 (Pacific Daylight Time) Design considerations when using programmable integer-N PLL ICs

Tue Jun 30 2009 22:06:33 GMT-0700 (Pacific Daylight Time) Rapid debug of serial buses in FPGAs

Mon Jun 01 2009 02:36:54 GMT-0700 (Pacific Daylight Time) Programmable clock management increases source synchronous throughput

Thu Apr 23 2009 22:15:34 GMT-0700 (Pacific Daylight Time) Top 10 tips to minimize power consumption when designing with FPGAs

Tue Apr 14 2009 13:01:56 GMT+0800 (China Standard Time) Using an interface wrapper module to simplify implementing PCIe on FPGAs

Wed Mar 11 2009 22:54:28 PDT How to detect solder joint faults in operating FPGAs in real time

Wed Mar 11 2009 22:54:06 PDT How to reduce power consumption in CPLD designs with power supply cycling

Sun Mar 1 2009 22:05:44 UTC+0800 How to control analog output from a CPLD using a pulse width modulator

Wed Feb 4 2009 09:31:35 UTC+0800 Xilinx FPGA introductions hint at new realities 1. One (trend) is the emphasis on density rather than performance. In moving to the new families Xilinx has slightly altered their logic-cell arrangement so that a logic slice comprises four six-input look-up tables (LUTs) and eight flipflops. This compares to four LUTs and four flops in the previous generation. 2. Another noteworthy point is the growing importance of high-speed serial transceiver performance. But the LXT also adds—unusually for a low-priced FPGA family—high-speed serial resources: up to eight low-power 3.2 Gbit/s transceivers, four hard-wired memory controllers, and one PCI-Express endpoint block. 3. A third interesting observation is the fragmentation of Xilinx's foundry strategy at the new node. Xilinx Director of Product Marketing Brent Przybus explained that the company chose to split production of the two families between UMC and Samsung... for both time-to-market and capacity reasons. 4. Finally, there is the question of power. But FPGAs still lag far behind ASICs and ASSPs in other means of power management. Voltage islands, dynamic power gating, dynamic voltage-frequency scaling, and threshold-voltage manipulation are still not available in the new Xilinx family. For that matter, of these techniques only programmable threshold-voltage control is available from Altera, and none of the techniques is supported by Xilinx. 5. Xilinx President and CEO Moshe Gavrielov sees many potential new users coming into the FPGA world, not from the ranks of experienced FPGA designers or even ASIC designers, but from the realm of software and systems engineering. In his vision, the FPGA becomes nearly a slate on which systems designers can write a systems-level design, without concerning themselves with the details of implementation. It is a bold, unifying vision that must contend carefully with the reality of the need for fine-grained control over the implementation at some points in many designs.

Tue Jan 20 2009 15:16:44 UTC+0800 Using yesterday's methodologies to design today's multi-FPGA systems is a recipe for disaster

Tue Jan 20 2009 15:15:55 UTC+0800 Tips and Tricks: Using FPGAs in reliable automotive system design

Tue Jan 20 2009 15:15:12 UTC+0800 PRODUCT HOW-TO: Taking the delay out of your multicore design's intra-chip interconnections

Tue Jan 20 2009 14:43:39 UTC+0800 Backplane tutorial: RapidIO, PCIe and Ethernet

Tue Jan 20 2009 14:43:16 UTC+0800 How to transform video SerDes from a nightmare to a dream

Tue Jan 20 2009 14:41:11 UTC+0800 Free Spice software exploits multicore processors

Thu Dec 4 2008 18:19:04 UTC+0800 Video processing pipeline design As in a RISC processor, a key goal for the video pipeline designer is to balance the stages.

Wed Dec 3 2008 18:06:32 UTC+0800 High-Performance SerDes Module with Easy FPGA Interface and Cable Detect

Sun Nov 30 2008 09:30:22 UTC+0800 How to improve FPGA-based ASIC prototyping with SystemVerilog

Sun Nov 30 2008 09:28:43 UTC+0800 Programmable logic use in handsets--The basics

Wed Sep 17 2008 22:29:34 UTC+0800 Reducing Power Consumption in a Fiber Channel Switch

Wed Sep 17 2008 22:28:01 UTC+0800 Product How-To: Building a configurable embedded processor - From Impulse C to FPGA

Fri Aug 29 2008 12:40:57 UTC+0800 Bridging options enable FPGA-based configurable computing

Thu Aug 28 2008 12:39:21 UTC+0800 Verilog versus VHDL (which is best?)

Thu Aug 28 2008 12:38:56 UTC+0800 How to give crime-fighters a flexible, high-performance edge with programmable logic

Tue Aug 26 2008 20:32:31 UTC+0800 Flexible I/O structure allows MCUs to have 'soft' I/O functions

Tue Aug 26 2008 20:31:35 UTC+0800 How to use CPLDs to manage average power consumption in portable applications

Tue Aug 26 2008 20:28:23 UTC+0800 How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)

Tue Aug 26 2008 20:21:19 UTC+0800 Algorithmic synthesis improves designers' efficiency

Tue Aug 26 2008 20:19:49 UTC+0800 Using FPGAs to improve your wireless subsystem's performance

Mon Aug 25 2008 22:19:46 UTC+0800 Tech Tutorial: Microcontroller design in FPGAs

Tue Aug 12 2008 06:50:24 UTC+0800 How to interface FPGAs to microcontrollers 随着FPGA的应用日益广泛，这篇文章介绍的内容已经成为FPGA设计者的一项基本功了。

Sun Jun 29 2008 21:15:59 UTC+0800 Single Flow for Interconnecting IP

Sun Jun 29 2008 21:16:40 UTC+0800 Timing-driven Simulink FPGA synthesis

Sun Jun 29 2008 21:22:42 UTC+0800 Got the BGA Blues?

Sat Jul 12 2008 16:54:50 UTC+0800 Tip of the Week---Simple power supply for FPGAs

Thu Jul 10 2008 21:20:56 UTC+0800 How to simplify power design development and evaluation for FPGA-based systems

PCB prototypes add value in the design process

Swapping bits improves performance of FPGA-PWM counters

How to enhance signal integrity in high density FPGA based designs

    一篇关于如何测试高密度引脚FPGA之间电路连通性的文章。

    FPGA的可编程特性使得这样的测试成为可能，FPGA与CPU连接电路的连通性恐怕就不这么好测试。

Digital Signal Processing Tricks - Frequency Translation without multiplication

FPGAs for motor control applications

    在LP做研究生课题时，用到了dsp56f805数字信号控制器，这款芯片一个主要应用领域就是电机控制，此外还有语音信号处理。片上的一个外设就是quadrature encoder，当时没看懂。在这篇文章里就介绍了quadrature encoder的应用。

Maximizing Performance and Reliability of FSMs with Precision Synthesis

    先放在这里，抽空读一下，把要点摘抄出来。

CVS Version Management in HDL Designer Series

    CVS是工程开发必不可少的工具，我在工作中一直使用。曾经用Tcl开发过几个自动上传下载并编译执行的脚本。

    这篇文章介绍了CVS在HDL Designer中的使用，介绍的原则应该可以用于Quartus II工作环境。可以考虑用Tcl开发，然后在Quartus II工作界面上添加自定义的Tcl按钮。

How to prototype your ASIC, SoC, or ASSP using FPGAs

FPGA是ASIC设计者的一道普通难题？

接口芯片：逻辑与严酷现实之间

FPGA设计的验证技术及应用原则

Interfacing FPGAs to DDR3 SDRAM memories

Guidance for Accurately Benchmarking FPGAs。鹬蚌相争，渔人得利。行业巨头的竞争产生了这样的文档。我可以按照文档的原意使用之，也可以把这篇文档作为在两个厂商之间转换设计的指导文档，也可以用作榨取器件性能的指导文档。

Advantages of the Virtex-5 FPGA 6-Input LUT Architecture。反唇相讥，针锋相对。竞争就是这样的。通过这篇文档，看到Xilinx器件相对于Altera器件的一大优势是LUT和FF可以分开使用，至少部分是这样的；不像Altera的，单独用LUT（组合逻辑）或单独用FF（时序逻辑）是很吃亏的。

Plugging hardware-based compression into a server

跨越异步时钟边界传输数据的解决方案骨灰级的前辈写的文章，此人拥有关于FIFO的多个专利。英文原文在此Moving Data across Asynchronous Clock Boundaries；此人的一篇Gray计数器专利在此Method and system for gray-coding counting，一定要拜读一下。

RTL for Z8000 series CPU?几位骨灰级前辈的跑题讨论。想俺当初毕设就是改写了一款8051的RTL，当时还真为专利、侵权的问题考虑了很多。

Digital Design with just one clock at one edge这个论坛上有太多的好东西了，惊喜！

SPI software coding

Surprise, surprise: Intermittent power-on reset problem reveals decades-old secret of 8052从一接触51，就发现PIO端口的电路设计很麻烦，尤其像2051这样的mini版。这篇文章给出了一个P0口使用的注意事项，以及误用后的电路表现。

Only Code Has Value?

Do engineers really do R&D?预研项目和工程项目确实有很大的差异。制定时间表是立项的重要内容。制定得准确与否，是立项工作质量的判断标准。“小步快跑”，滚动式开发是个不错的方式。

Mon Jan 7 2008 11:01:54 UTC+0800 Get research out of development上一篇文章的系列二

Common mistakes in electronic design电子系统的可靠性设计，在设计PCB时，这些经验是很宝贵的，甚至是难得的。

Tue Dec 18 2007 09:57:20 My Gray Code article saves the day!真正的技术实践。不过，解决SSN这一问题的方法可能不只是减少信号的SS（瞬时翻转），减小信号的驱动电流应该起到同样的作用。

Wed Dec 19 2007 09:10:37 Using DCFIFO for Data Transfer between Asynchronous Clock DomainsAltera 第一次给出了完整的跨时钟域数据传输解决方案，够权威。

AN 42: Metastability in Altera Devices

嵌入式系统原理文章汇总

Tue Mar 09 2010 09:34:57 GMT+0800 (China Standard Time) Ensuring the thermal integrity of your IC package/PC board design

Thu Feb 25 2010 13:58:36 GMT+0800 (China Standard Time) The evolution of the general-purpose oscilloscope The move from analog to digital was just the first step in a long line of enhancements

Thu Feb 25 2010 13:56:56 GMT+0800 (China Standard Time) Hardware Testing Board testing is harder than you think, but there are solutions

Sun Feb 07 2010 23:43:50 GMT-0800 (Pacific Standard Time) The differential-signal advantage for communications system design Understand how differential signal chains and architectures can improve system performance in challenging applications

Tue Jan 26 2010 21:11:00 GMT-0800 (Pacific Standard Time) Isolate your interface to communicate safely and better Understand how galvanic isolation of signal and power can improve performance and safety of basic interfaces such as RS-485

Tue Jan 26 2010 21:09:55 GMT-0800 (Pacific Standard Time) S-parameters Without Tears Understand this increasingly critical measurement and its interpretations

Tue Jan 26 2010 21:07:55 GMT-0800 (Pacific Standard Time) System level transient voltage protection--Five in-depth answers to ESD questions  The challenge of protecting today's systems from transient threats is more complex than ever before. Here are answers to important questions that can ensure that a system is adequately safeguarded against these damaging electrical transient threats.

Fri Jan 08 2010 01:56:27 GMT-0800 (Pacific Standard Time) A new approach to improving system performance

Thu Oct 08 2009 11:39:27 GMT+0800 Improvement of libpcap for lossless packet capturing in Linux using PF_RING kernel patch

Thu Oct 08 2009 11:38:17 GMT+0800 An Excelent fit, Sir!

Wed Sep 30 2009 19:40:56 GMT+0800 Using your MCU's time processing unit as an on-chip logic analyzer

Mon Sep 28 2009 22:14:04 GMT-0700 (Pacific Daylight Time) How to effectively use fan trays in electronic systems

Sun Sep 20 2009 21:47:52 GMT-0700 (Pacific Daylight Time) Fundamentals of Booting for Embedded Processors

Wed Aug 12 2009 22:26:19 GMT-0700 (Pacific Daylight Time) Debugging software/firmware using trace function re-usable components

Wed Aug 12 2009 22:10:42 GMT-0700 (Pacific Daylight Time) Serial Boot: An alternative way of booting SoC externally

Wed Aug 12 2009 22:09:55 GMT-0700 (Pacific Daylight Time) Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7

Mon Jul 27 2009 22:39:53 GMT-0700 (Pacific Daylight Time) What makes embedded different?

Mon Jun 01 2009 02:39:12 GMT-0700 (Pacific Daylight Time) The LIN-Bus and its contribution to eco-friendly vehicles

Mon Jun 01 2009 02:33:48 GMT-0700 (Pacific Daylight Time) Improving performance for dynamic memory allocation

Mon Jun 01 2009 02:03:48 GMT-0700 (Pacific Daylight Time) Protect PoE interfaces from differential-mode transient voltage threats

Mon Jun 01 2009 02:01:13 GMT-0700 (Pacific Daylight Time) Capturing and Debugging System Crashes

Tue Apr 14 2009 12:59:59 GMT+0800 (China Standard Time) Optimization of current-limiting solutions for USB 3.0

Tue Apr 14 2009 12:56:27 GMT+0800 (China Standard Time) Using software flashing to secure embedded device updates

Tue Apr 14 2009 12:55:36 GMT+0800 (China Standard Time) Who Killed My Battery?

Thu Mar 26 2009 22:10:01 GMT-0700 (Pacific Daylight Time) Memory system tradeoffs: embedded DRAM in SoCs, Chip-on-Board, multichip packages or memory modules

Mon Mar 16 2009 22:48:26 PDT Mysterious data errors "It took more time to build the equipment than it did to find the problem!"    "As it turned out, the engineers who designed the system did an excellent job, but they apparently had little or no communication with the person who did the PCB design."

Mon Feb 23 2009 13:29:47 UTC+0800 How to measure audio quality in portable media players

Tue Jan 20 2009 15:29:59 UTC+0800 Filter banks, part 1: Principles and design techniques

Thu Dec 11 2008 13:21:55 UTC+0800 The software is the product

Sun Nov 30 2008 09:26:04 UTC+0800 Open source in consumer electronics: What, why and how

Sun Nov 9 2008 08:48:44 UTC+0800 Use Pre-Configured Device Drivers (PCD) to reduce embedded system memory footprint A very efficient and practical way!

Sun Nov 9 2008 08:47:00 UTC+0800 Need a watchdog for improved system fault tolerance?

Fri Oct 3 2008 23:30:55 UTC+0800 Don't believe everything you hear about RTOSes

Fri Oct 3 2008 23:30:14 UTC+0800 How to transform silicon with dynamic reconfiguration

Wed Sep 17 2008 22:31:32 UTC+0800 Dynamic reconfiguration is transforming the embedded world

Wed Sep 17 2008 22:30:33 UTC+0800 Expanding the Embedded Universe: Migrating From IPv4 to IPv6

Fri Aug 29 2008 12:34:25 UTC+0800 Image capture and processing challenges--and solutions--in portable designs

Thu Aug 28 2008 12:41:55 UTC+0800 In-system programming of FLASH via control unit application

Thu Aug 28 2008 12:40:25 UTC+0800 A primer on extending serial ports in embedded designs

Sat Aug 23 2008 15:45:41 UTC+0800 Embedded Books Reading Room

Sun Aug 17 2008 14:17:06 UTC+0800 HDMI's Lip Sync and audio-video synchronization for broadcast and home video

Sat Jun 14 2008 08:20:41 UTC+0800 To accelerate or not to accelerate...

Sat Jun 14 2008 09:02:01 UTC+0800 Tutorial on 802.11n PHY layer

Sun Jun 29 2008 20:01:40 UTC+0800 Design Challenges Drive Need for New Routing Architecture

Sun Jun 29 2008 20:12:37 UTC+0800 Leveraging virtual hardware platforms for embedded software validation

Sun Jun 29 2008 20:15:19 UTC+0800 Microkernels rule!

Sun Jun 29 2008 20:16:16 UTC+0800 Benchmarking basics

Wed Dec 19 2007 13:09:26  Jitter, Noise, and Signal Integrity at High-Speed: A Tutorial

Jitter peaking and PLLs

Tue Jan 8 2008 17:38:47 UTC+0800 错误检测与纠正电路的设计与实现

Wed Jan 23 2008 13:49:48 UTC+0800 MEN Micro extends universal-submodule concept SOPC的新应用——总线桥

Fri Jan 25 2008 15:37:30 UTC+0800 8-bit microcontroller implements digital lowpass filter

Roll back the lead-free initiative: 12 ROHS myths By Howard Johnson, PhD -- EDN, 9/13/2007

Distributed linear regulators increase output currentTop-down DSP design for FPGAs

FPGA的青春之泉——安全的现场升级技术

Demystifying multithreading and multi-core

What does '45-nm' mean, anyway?

HDMI接口噪声的抑制方法难得一见的图文并茂的好文章，内容又清晰，分析又准确。

A New Approach to In-System Silicon Validation and Debug

Selecting op amps运算放大器一直是令我困惑的模拟器件。

Design tip: Model instruments to improve signal integrity simulation模型与真实世界的近似程度决定了模拟的可信性。

SAS (Serial Attached SCSI) 技术详解

PCI Express总线技术白皮书

Ethernet and Multimedia Applications - The History and the Future

行业趋势文章汇总

Thu Mar 11 2010 13:19:10 GMT+0800 (China Standard Time) Viewpoint: Your future is programmable

集成电路业：最缺领军人才

中国IT设计向暴富说“NO”

ARM and Altera
Why You Should Care 越来越有趣了

PRODUCT HOW-TO: Use ARM DBX hardware extensions to accelerate Java in space-constrained embedded apps在一期ARM IQ上看到过类似的文章，细读了一遍，感想颇丰，有机会一定要整理出来。Java虚拟机的硬件实现、CPU的指令集扩展、Java字节码的模拟执行、动态编译技术，这些概念太有趣了。

中国汽车电子产业迅猛发展

Viewpoint: RTL-ers should move to ESLRTL 仍然有用武之地，而ESL的学习和掌握又不是那么简单，盲目跟风不可取；话虽如此，从个人技术发展和企业的长期绩效来看，掌握和应用ESL又是大势所趋。个人的技术发展和行业的技术发展应该有相同的模式，先掌握RTL，基础要扎实，然后学习ESL，平稳过渡。跳跃发展要不得。

Mechatronics-based embedded design

Accellera VHDL Standard

Scope: IEDM, software-debugging via hardware

龙芯百万量级规模生产启动 凭什么走向世界

FPGA奔向45纳米

The changing outsourcing landscape in China设计外包不是新闻了，看看国内谁在做？

IBM licenses 45-nm bulk CMOS process to SMIC我们国家也有能力生产这么前沿的芯片了，如何利用好它？

Innovation as differentiation: A fireside chat with Wim RoelandtsXilinx的老CEO能否预言成真？

Chip makers must shift from fabs to systems

Wed Jan 23 2008 09:35:44 UTC+0800 Book delves into serial ports; they never were “obsolete”我很久以前买过一本《串行端口大全》，现在出第二版了。看来串口技术的生命力真的很强。

Wed Jan 23 2008 09:36:59 UTC+0800 IPextreme Core Store simplifies IP shopping Let's go IP shopping！

Wed Jan 23 2008 09:43:08 UTC+0800 Wed Jan 23 2008盛美半导体落户张江 芯片设备垄断有望打破 Finally！

Mon Feb 25 2008 13:13:11 UTC+0800 As SOCs grow, test-and-measurement instruments move on-chip

Tue Mar 4 2008 17:03:19 UTC+0800 Sun to guide IC curriculum development for China’s  universities 多好的条件，让人羡慕，孩子们好好学啊。

国内外专利新闻汇总

Sun Dec 27 2009 22:12:57 GMT-0800 (Pacific Standard Time) Seven hard lessons on writing a grant proposal

Sun Dec 27 2009 19:03:53 GMT-0800 (Pacific Standard Time) Intel, AMD, Patents, and Punishment

Wed Nov 18 2009 00:05:37 GMT-0800 (Pacific Standard Time) Intel, AMD, Patents, and Punishment

Thu Nov 12 2009 16:56:25 GMT-0800 (Pacific Standard Time) Chinese Knockoffs Move Beyond Gucci Bags

Mon Aug 31 2009 01:38:58 GMT-0700 (Pacific Daylight Time) Engineer seeks $60 million bonus from Atmel

Wed Jul 22 2009 20:48:34 GMT-0700 (Pacific Daylight Time) Report attacks post-grant patent review

Tue Jun 30 2009 21:43:29 GMT-0700 (Pacific Daylight Time) Keep innovating in the downturn

Tue Jun 09 2009 21:51:24 GMT-0700 (Pacific Daylight Time) Prep patents with reverse engineering in mind

Mon Jun 01 2009 02:24:22 GMT-0700 (Pacific Daylight Time) Video: Intel, startup face off in patent debate

Mon Jun 01 2009 02:23:35 GMT-0700 (Pacific Daylight Time) EU patent research prepares for commercialization

Sat May 30 2009 22:36:25 GMT-0700 (Pacific Daylight Time) AMEC gains legal victory over Applied

Tue May 05 2009 22:01:09 GMT-0700 (Pacific Daylight Time) 我国LED产业面临重大专利风险

Tue Apr 28 2009 22:24:42 GMT-0700 (Pacific Daylight Time) Qualcomm to pay Broadcom $891M to settle patent disputes

Tue Apr 21 2009 12:49:08 GMT+0800 (China Standard Time) Opinion: Engineers should stage a patent strike

Tue Apr 21 2009 12:48:18 GMT+0800 (China Standard Time) Protecting software IP: what engineers need to know

Tue Apr 14 2009 12:52:18 GMT+0800 (China Standard Time) Altera claims legal victory over Zilog

Sun Mar 29 2009 19:47:05 GMT-0700 (Pacific Daylight Time) 乙肝用药强制国产化刻不容缓

Tue Mar 17 2009 04:11:23 PDT 中兴全球专利申请数达17000项 2000人研发4G

Tue Jan 20 2009 14:37:04 UTC+0800 U.S. lead in patents narrows

Wed Dec 10 2008 13:30:32 UTC+0800 Amino takes MPEG-2 license, settles patent disputes

Wed Dec 10 2008 13:28:24 UTC+0800 IEEE joins move to patent pools

Mon Dec 8 2008 12:46:43 UTC+0800 Microsemi probes CEO's academic credentials

Thu Nov 27 2008 13:22:13 UTC+0800 Cisco, IBM join subscription patent service

Thu Nov 27 2008 13:21:45 UTC+0800 Firm sues Apple, claims iPhone infringes patent

Mon Sep 22 2008 12:06:11 UTC+0800 ITC to look into patent claims over Nintendo's Wii

Sat Sep 6 2008 08:50:25 UTC+0800 FPGA architecture patent granted to systems and IP company

Thu Aug 28 2008 12:31:15 UTC+0800 Altera files suit against Zilog

Sat Aug 23 2008 00:49:59 UTC+0800 Let's Abolish All Patents

Sat Aug 23 2008 00:15:44 UTC+0800 My IP-Brain for Rent

Mon Jul 14 2008 12:34:32 UTC+0800 Rambus claims Nvidia infringes patents

Sat Jul 12 2008 16:08:51 UTC+0800 Nokia, InterDigital settle some IP disputes

Sat Jul 12 2008 16:07:34 UTC+0800 Patent pools may flow in wake of latest alliance

House passes controversial patent reform bill

Patent litigation on the rise in semi sector，专利诉讼案日益增加 半导体行业缘何爱惹“官司”？

Cadence extends IP licensing with Microsoft

Competing in the FPGA physical synthesis market

Under the Hood: Silicon in autos driving patent plans

Configurable advanced technology attachment/integrated drive electronics host controller with programmable timing registers that store timing parameters that control communications

Wed Jan 2 2008 13:29:41 UTC+0800 U.S. patent office looking for prior art on IBM patent application

Qualcomm, attorneys rebuked for withholding documents in Broadcom case

Memory goes multicore

Inventors Transform Possibilities into Patented Reality，turning ideas into patents and patent applications

Sat May 3 2008 15:07:47 UTC+0800 U.S. patent chief: applications up, quality down

Sat May 3 2008 15:08:02 UTC+0800 Keynote speakers differ on the health of the US patent system

中国公司积极应对海外诉讼很有必要

知识产权战略：推动经济持续增长的力量

抵制专有权滥用可实现双赢

从手机新专利技术看未来手机

ARM cleared in MMP patent appeal case

Intellectual Property: Joy and Sorrow

Rules need a re-write, say IP experts at forum

Accelerating development and lowering risk

Jury rules for Broadcom in patent case against Qualcomm

相关资源：PatentStorm: U.S. Patents

在PatentStorm上搜索“ata + disk”的专利

中华人民共和国国家知识产权局

台湾省专利公报资料库 可以申请临时帐号进行专利查询

United States Patent and Trademark Office

验证和建模方法文章汇总

Aldec Events

Aldec Design and Verification Newsletter

Thu Mar 11 2010 13:34:19 GMT+0800 (China Standard Time) ICE debugging: The end of the battleship game

Mon Mar 01 2010 09:54:16 GMT+0800 (China Standard Time) 浮点模型的定点化到产品级代码的生成

Thu Feb 25 2010 14:06:46 GMT+0800 (China Standard Time) Reducing Costs, Risks, Time to Market with Virtualized Systems Development

Thu Feb 25 2010 14:01:50 GMT+0800 (China Standard Time) Help — All of my simulations are passing!

Thu Feb 25 2010 14:00:35 GMT+0800 (China Standard Time) Guidelines for complex SoC verification A plan-manage-execute approach to verification

Thu Feb 25 2010 13:51:46 GMT+0800 (China Standard Time) High-level synthesis, verification and language

Sun Feb 07 2010 18:18:17 GMT-0800 (Pacific Standard Time) Layering it on--a new approach to automating system tests

Sun Feb 07 2010 18:17:48 GMT-0800 (Pacific Standard Time) Researchers propose commonsense plan to improve verification process

Sun Feb 07 2010 18:16:59 GMT-0800 (Pacific Standard Time) Managing Complex SoC verification using plan based verification techniques

Thu Feb 04 2010 17:22:47 GMT-0800 (Pacific Standard Time) Debugging and analysis with SystemVerilog test bench

Thu Feb 04 2010 17:21:31 GMT-0800 (Pacific Standard Time) Can C beat RTL?

Wed Feb 03 2010 18:38:01 GMT-0800 (Pacific Standard Time) Formal verification with constraints — It doesn't have to be like tightrope walking

Tue Jan 26 2010 21:03:46 GMT-0800 (Pacific Standard Time) Embedded system virtualization for executable specifications and use case modeling

Sun Jan 24 2010 21:33:35 GMT-0800 (Pacific Standard Time) Applying virtual system integration and test to validate requirements and verify designs

Sun Jan 24 2010 21:32:48 GMT-0800 (Pacific Standard Time) Early verification cuts design time and cost in algorithm-intensive systems

Tue Jan 19 2010 21:06:26 GMT-0800 (Pacific Standard Time) Study gives mixed marks to high-level synthesis

Sun Jan 17 2010 21:20:00 GMT-0800 (Pacific Standard Time) Low power LDPC decoder created using high level synthesis

Sun Jan 17 2010 21:17:01 GMT-0800 (Pacific Standard Time) A real solution for mixed signal SoC verification

Fri Jan 08 2010 01:59:35 GMT-0800 (Pacific Standard Time) SOFTWARE TOOLS - PetaLogix Launches First Linux SDK for FPGA-based Embedded Systems

Fri Jan 08 2010 01:57:34 GMT-0800 (Pacific Standard Time) Firms integrate toolkit for hardware/software co-simulation

Fri Jan 08 2010 01:49:48 GMT-0800 (Pacific Standard Time) Low power design is here to stay

Tue Jan 05 2010 17:27:20 GMT-0800 (Pacific Standard Time) A unified, scalable SystemVerilog approach to chip and subsystem verification

Tue Jan 05 2010 17:14:56 GMT-0800 (Pacific Standard Time) Using OVM to reuse vital verification knowledge

Mon Dec 28 2009 00:30:22 GMT-0800 (Pacific Standard Time) GUI testing: exposing visual bugs

Mon Dec 28 2009 00:28:14 GMT-0800 (Pacific Standard Time) ABV: Is there a there there?

Sun Dec 27 2009 22:13:53 GMT-0800 (Pacific Standard Time) Improve functional verification quality with mutation-based code coverage

Mon Nov 16 2009 21:09:56 GMT-0800 (Pacific Standard Time) The Use Of Assertions A new study shows the power of seeding your code with assertions

Tue Nov 10 2009 21:14:41 GMT-0800 (Pacific Standard Time) The best of both worlds: Optimizing OCP slave memory behavior

Wed Oct 28 2009 18:24:18 GMT-0700 (Pacific Daylight Time) Why verification engineers are like football players

Thu Oct 22 2009 17:49:17 GMT-0700 (Pacific Daylight Time) FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs

Mon Oct 19 2009 19:59:48 GMT-0700 (Pacific Daylight Time) FPGA design and verification in mechatronic applications

Sat Oct 17 2009 08:35:46 GMT+0800 Are We There Yet? New Ways to Reduce Verification Time

Thu Oct 08 2009 11:31:00 GMT+0800 Best practices interoperability guide approved for IP verification

Sat Oct 03 2009 10:25:41 GMT+0800 Using Tcl to create a virtual component in Verilog

Sat Oct 03 2009 10:24:31 GMT+0800 A brief introduction to the TCL Scripting Language

Thu Oct 01 2009 09:05:41 GMT+0800 The Myriad Challenges of Testing Automotive Electronics

Mon Sep 28 2009 22:22:57 GMT-0700 (Pacific Daylight Time) Using CMMI for software requirements testing in system design & development

Mon Sep 28 2009 22:11:15 GMT-0700 (Pacific Daylight Time) Moving model-based development into safety-critical embedded applications

Mon Sep 28 2009 22:09:18 GMT-0700 (Pacific Daylight Time) Using platform independent models to proliferate code across multiple application environments

Thu Sep 24 2009 20:14:31 GMT-0700 (Pacific Daylight Time) System testing of digital camera devices as reverse engineering

Sun Sep 20 2009 21:56:55 GMT-0700 (Pacific Daylight Time) OCP-IP SOLV eases SoC verification

Sun Sep 20 2009 21:53:59 GMT-0700 (Pacific Daylight Time) System testing of digital camera devices as reverse engineering

Tue Aug 18 2009 02:18:26 GMT-0700 (Pacific Daylight Time) Virtual testing with model-based design

Wed Aug 12 2009 22:24:06 GMT-0700 (Pacific Daylight Time) Viewpoint: Capture OCP systems in IP-XACT 1.4

Fri Aug 07 2009 02:53:28 GMT-0700 (Pacific Daylight Time) Visual Modeling of Complex Reactive Systems with Harel UML StateCharts

Mon Jul 27 2009 22:59:56 GMT-0700 (Pacific Daylight Time) Early design verification with virtual system integration and simulation

Mon Jul 27 2009 22:59:13 GMT-0700 (Pacific Daylight Time) Unleash the power of formal technology for CDC verification

Tue Jun 30 2009 21:55:49 GMT-0700 (Pacific Daylight Time) Mentor adds support for control logic to Catapult C

Tue Jun 30 2009 21:55:03 GMT-0700 (Pacific Daylight Time) Forte beefs up high-level synthesis tool

Sun Jun 21 2009 21:44:01 GMT-0700 (Pacific Daylight Time) Managing an adaptive verification environment with OVM

Wed Jun 17 2009 00:19:25 GMT-0700 (Pacific Daylight Time) Learn To Manage All Kinds of Complexity With SystemC

Tue Jun 16 2009 22:15:13 GMT-0700 (Pacific Daylight Time) Get an optimized flow on an AMBA-based design

Sun Jun 14 2009 18:31:37 GMT-0700 (Pacific Daylight Time) Troubleshooting a transaction-level model

Tue Jun 09 2009 21:56:04 GMT-0700 (Pacific Daylight Time) Taking the guesswork out of timing in real-time software systems

Tue Jun 09 2009 21:50:13 GMT-0700 (Pacific Daylight Time) Model-based design helps aerospace engineers improve design quality

Mon Jun 01 2009 02:40:57 GMT-0700 (Pacific Daylight Time) Using Algorithmic Synthesis to Design Fourth Generation Cellular Hardware Accelerators

Mon Jun 01 2009 02:17:20 GMT-0700 (Pacific Daylight Time) Using advanced logging techniques to debug & test SystemVerilog HDL code

Mon May 04 2009 22:02:47 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis: Anesthesia ventilator evaluation

Mon May 04 2009 22:02:14 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis - Defining a Profile

Mon May 04 2009 22:01:02 GMT-0700 (Pacific Daylight Time) Build Safety-Critical Designs with UML-based Fault Tree Analysis - The basics

Mon May 04 2009 21:49:16 GMT-0700 (Pacific Daylight Time) Visualizing, Analyzing and Debugging SystemVerilog Testbench Environments

Mon May 04 2009 21:47:51 GMT-0700 (Pacific Daylight Time) Using OCP and Coherence Extensions to Support System—Level Cache Coherence

Thu Apr 23 2009 22:17:43 GMT-0700 (Pacific Daylight Time) No Government Bailout for Poor Test Planning

Tue Apr 21 2009 12:50:27 GMT+0800 (China Standard Time) Hardware Design Requires Hardware Design Languages

Sun Apr 19 2009 22:26:17 GMT-0700 (Pacific Daylight Time) Cornering Those Corner Case Bugs: Functional Coverage On Multiple Interfaces

Sun Apr 19 2009 22:22:17 GMT-0700 (Pacific Daylight Time) Finding defects using Holzmann's "Power of 10" rules for writing safety critical code

Sun Apr 19 2009 22:20:21 GMT-0700 (Pacific Daylight Time) What you need to know about automated testing and simulation

Tue Apr 14 2009 13:06:25 GMT+0800 (China Standard Time) Using finite state machines to design software

Tue Apr 14 2009 13:03:38 GMT+0800 (China Standard Time) SOFTWARE TOOLS: New suite provides End-to-End Software Verification

Tue Apr 14 2009 13:02:51 GMT+0800 (China Standard Time) Overcome LTE PHY challenges using ESL design

Sun Mar 29 2009 22:09:59 GMT-0700 (Pacific Daylight Time) Design quality enhances company survival
Like it or not, semiconductor design in the early 21st century has more in common with an assembly line than a research lab. That they function smoothly is only possible because manufacturing engineers know, in advance, exactly how they define quality, and they continuously monitor and correct quality problems, at the source. This continuous monitoring is often labeled continuous quality control (CQC). Closed-loop and group-wide feedback must be a non-negotiable component of any practical CQC process. The broader your range of regressions, the better you will control your design program. But consider also the personal benefits to a design team lead or manager. Executives value managers who are clearly in control even, paradoxically, if their projects are not always successful. They know that, over the long haul, disciplined managers deliver better results on average than their peers.

Fri Mar 20 2009 23:37:20 GMT+0800 A SystemC-Based RTOS Model for Multiprocessor Systems-on-Chips

Mon Mar 02 2009 21:16:29 GMT-0800 (Pacific Standard Time) Functional qualification: a technical brief

Mon Feb 16 2009 18:09:19 UTC+0800 Mentor Graphics inFact Tool provides plug-and-play interoperability with OVM

Mon Feb 16 2009 18:08:43 UTC+0800 ESL: Where are we and where we are going

Mon Feb 16 2009 18:08:11 UTC+0800 Abstraction and Control-Dominated Hardware Designs

Wed Feb 4 2009 15:16:50 UTC+0800 How SLEC improves functional verification

Thu Jan 22 2009 18:14:59 UTC+0800 Mentor unveils TLM 2.0 design flow

Tue Jan 20 2009 15:05:57 UTC+0800 The Virtual Vehicle: Part 1 - In-vehicle networking simulation and analysis

Tue Jan 20 2009 15:04:57 UTC+0800 Architecting the OCP uVC verification component

Tue Jan 20 2009 15:04:29 UTC+0800 Doing ESL system validation using transactors

Tue Jan 20 2009 15:03:38 UTC+0800 An application modeling & hardware description for network-on-chip benchmarking

Tue Dec 23 2008 18:01:02 UTC+0800 Using requirements based testing to find defects in your software builds

Sun Dec 14 2008 21:11:14 UTC+0800 Adapt standard tests to non-standard devices: Automotive qualification of a MEMS-based sensor system

Thu Nov 27 2008 13:14:44 UTC+0800 Unified Verification for Hardware and Embedded Software Developers

Sun Nov 9 2008 08:19:58 UTC+0800 Borrowing from software to use SystemVerilog test bench debug & analysis

Thu Aug 28 2008 12:34:53 UTC+0800 Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions

Wed Aug 27 2008 12:46:40 UTC+0800 TCL Drives C Drives SystemVerilog - An Overview

Wed Aug 27 2008 12:46:49 UTC+0800 Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation - The Details

Tue Aug 26 2008 20:40:04 UTC+0800 Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor

Introduction to and Regression Test for OCP System介绍了TLM、OCP-IP、Channels、Regression Test等概念，值得一读。

Accelerating Functional VerificationCadence的GUI功能验证工具。

Verification Horizons A QUARTERLY PUBLICATION OF MENTOR GRAPHICS Q4 '07 - VOL. 3, ISSUE 4OVM提出以来，Mentor的第一批文章。

I Know What You Didn't Verify Last Summer!

The Great EDA Cover-up

Cadence makes logic verification OVM-savvy

A revolution in functional verification

Applying Constrained-Random Verification to Microprocessors

Efficient testbench implementation for verification proposed by Synopsys staffer

Verification Platform for Complex Designs

Open Verification Methodology ready for download from Cadence, Mentor

Why we need an analog design flow that's like digital now

验证计划报表工具VMM Planner

Commentary: 'Open' is (not) just a four-letter word the meaning of open.

VMM application packages: the next level of productivity

Tue Feb 19 2008 14:09:45 UTC+0800 Mentor Delivers Higher Verification Intelligence

Tue Feb 26 2008 18:23:09 UTC+0800 Multi-language Functional Verification Coverage for Multi-site Projects

Wed Mar 5 2008 13:12:10 UTC+0800 Imperas donation forms open-source virtual platform initiative something like many a virtual machines, but open and free.

Tue Mar 18 2008 13:57:59 UTC+0800 FPGA设计的验证技术及应用原则，非常好的时序仿真指导原则。在以往的调试中我极力回避时序仿真，可以从这篇文章中借鉴一下时序仿真的操作！

Assertion分类：

Assertion Based Verification

Set of assertions serves multiple tools

OVL Made Easy for Assertion-Based Verification

Accellera Assertion Technical Committee

Assertions in Verilog

相关链接：OVM World：Open Verification Methodology

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