关于模拟设计的基本考虑

关于模拟设计的基本考虑

Basic Precautions and Tips that an Analog Designer Should Know.

很多时候，我们在初期设计或者优化电路时，满脑子想的都是性能如何能一点一点提高，而忽略了所谓的模拟设计的一些基本考虑；待到版图设计时已经晚矣。那个时候再去修改基本设计无疑是不值得，要么耗费精力，要们前功尽弃。作为教训，如果我们能够在设计初期，就带着这些基本考虑，那么在选择基本器件的时候，就会有的放矢，知道一个大概的合理的选取范围，有利于版图设计和优化。

1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low.

晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应。

2. Present art of analog design still uses the transistor in the saturation region. So one should always keep Vgs of the Transistor 30% above the Vt.

目前模拟设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%。

3. One should always split the big transistor into small transistors having width or length feature size < or = 15um.

应把大管分成小晶体管，使其宽/长特征尺寸<或=15um。

4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systematic Offset in the circuit.

电流镜电路的晶体管的w/l比应小于或等于5，以保证较好的Matching,否则会有系统失调。

5. One should make all the required pins in the schematic before generating the layout view. Because it’s difficult to add a pin in the layout view. All IO pins should be a metal2 pins whereas VDD and Ground should be metal1 pins

在电路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是比较困难的。所有的IO pin应该用metal2 pin，VDD和GND用metal1。

6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the transistor can be anything between Vt(Typical) -/+ 20%. So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. A transistor having Vt-20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It’s just a way to differentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are satisfied with the circuit performance with typical models than we check it in different process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too.

首先先用tt做电路仿真。考虑Vt有+20% (slow)和-20% (fast),需要对工艺角考虑，FF，SS，FS，SF。除Vt，其他工艺参数也会有变化。

7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coefficient and lower Sheet Resistance than well resistance So we choose the resistance type depending upon the requirements. Poly Capacitance has got a process variation of 10%.

多晶硅电阻大约有20%的工艺变化，而阱区电阻变化约为10%。但多晶硅电阻有较低的温度系数和低的方块电阻，应根据需要来选择电阻。多晶硅电容约有10%工艺变化。

8. One should also check the circuit performance with the temperature variation. We usually do it for the range of -40C to 85C.

需考虑温度变化对电路性能的影响，通常在-40C到85C范围。

9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells.

有覆盖金属层或阱区时，须考虑寄生电容。

10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors.

Layout中，所有晶体管统一摆放方向，使有相同的环境。

11. One should place all transistor in layout with a due care to the pin position before start routing them.

在对晶体管布局布线之前，考虑Pin的位置。

12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible.

尽量使用metal1横向布线，metal2纵向布线半导体。

13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly.

在互连用来传送电流时，不要用Poly来做互连。可以用poly做短的栅连接。

14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance.

避免金属在多晶硅栅上走线，会增加寄生电容。

15. Current in all the transistor and resistor part should flow in the same direction.

所有晶体管和电阻有相同的电流走向。

16. One should do the Power(VDD & GND) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance.

在最上层金属做电源（VDD和GND）布线。因为最上层金属通常更厚、更宽，因而电阻较小。

17. One should always merge drain and source of transistor (of same type) connected together.

merge连接的Source和Drain。

18. To minimize the process variation in the Resistor value one should always take the resistor’s width three to four times of the default value. we do it to decrease the value of differential of R(L)

为减小工艺变化对电阻影响，应使电阻的宽度为默认值的3-4倍半导体。

19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.

用金属覆盖电阻，避免wafer级测试时的损伤。

20. One should always make a Common Centroid structure for the matched transistor in the layout. Each differential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure. One may use the linear common centroid structure for the current mirror circuit.

对匹配的晶体管用共中心的结构

*差分对管，分割为4管，2*2排列，共中心

可用线形共中心

21. It’s advisable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching.

建议在电阻和电容周围作dummy。

22. One should always have a Guard Ring around the differential pair.

在差分对周围作保护环。

23. Always put a Guard Ring around the N-well and P-well.

在N阱和P阱作保护环。

24. Thumb rule for the metal current density is 0.8mA/um. It’s larger for the top most metal layer.

金属电流密度0.8mA/um，最上层金属可以更大半导体。

25. To avoid the Latch-up, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply (VDD) and PWELL should be connected to negative power supply (GND). Designers do it to make the leakage current small.

为避免Latch-up，应使PN结反偏，如N-Well应连到正电源，P-Well应连到负电源。这样可减小漏电。

26. It’s always a good practice to use an info-text layer to put the name of the device on the top of it in layout and have a net-name for every nets in schematic. Designer should put the pin name on the top of the pin with same metal-txt layer because hercuels takes the net-name from metal-txt only whereas Diva takes from the pin-name.

在layout中用info-text标明器件名称，在schematic中标明net。用相同的metal-txt层标明pin。

27. Cadence SPICE simulator take vdd! & gnd! as a global VDD and GND net i.e. any net ending with ‘ !’ is considered as a global net.

Cadence 模拟工具对以‘!’结尾的net认为全局net。

28. Transistor Equation: 基本晶体管方程

Id=(beta/2)*square(Vgs-Vt)

Gm=square root of(2Id*beta)

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关于电路中核心模块的电流供给处理

关于电路中核心模块的电流供给处理

关键词：偏置 电流镜 核心模块

在最近的一次设计中，非常遗憾地，我犯了一个很严重的错误，导致的结果就是PLL无法像预想的那样准确锁定，而且非常可惜的是芯片的可测点太少，无法准确确定问题来源。

归纳教训无外乎如下几点：

   1. 对于初次设计某模块电路，其核心部分的电流供给最好不要复杂化。因为如果所设计的复杂的片上偏置电路（电流产生基准）没有正常工作或失效，那么核心模块将由于电流供给不足而无法测试出真正的性能。妥善的做法是，在初次设计时，用最简单的并且外部可调的偏置为核心模块提供电流；二次设计时，加入经过验证的片上偏置电路，减少片外元件。

   2. 对于芯片设计，尽量多的考虑其可测性。在关键节点处预留测试点，加入Enable端口灵活控制各个模块，方便独立测试或工作；同时，有可能需要通过外部电源电压调节的测试点，需要考虑是否应该加ESD（默认各IO端口皆加ESD）；重要模块的可测性可以通过将某元件放置片外来予以调节。

   3. 核心模块的电流供给尽量避免使用大比例的电流镜来获得，若非要如此亦需注意考虑电流镜失配时核心电流的补偿手段，不然，由于PVT的不可预测的变化（超出工艺角的范围）将导致核心电流不足。电流镜本身的比例关系、版图对称性也应该给予足够的重视，平时多加练习与尝试。

   4. 规模稍大的芯片，需要在芯片设计初期就规划好各个模块失效对应的解决措施。如此次的PLL由于某个模块的偏置失效而无法正常工作就显得非常遗憾。应该考虑加入可切换的控制模块，当某个模块失效，通过控制信号可以切换到外部来提供相应的信号。这样不会由于某个模块的失效而导致无法测试剩余模块。

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集成电路设计领域之国际国内杂志与会议

集成电路设计领域之国际国内杂志与会议

chenpufeng@ime.ac.cn

Journal and Transaction:

IEEE Journal of Solid-State Circuits(JSSC)

IEEE Transactions on Very Large Scale Integration(VLSI) Systems

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Circuits and Devices Magazine

IEE Electronics Letters (EL)

Journal of Circuits, Systems, and Computers

Journal of Chinese Semiconductor

电子学报

固体电子学研究与进展

微电子学

电路与系统学报

电子与信息学报

Conference:

IEEE International Solid-State Circuits Conference (ISSCC)

IEEE Custom Integrated Circuits Conference (CICC)

ACM/IEEE Design Automation Conference (DAC)

IEEE/ACM International Conference on Computer Aided Design (ICCAD)

International Electron Devices Meeting (IEDM)

IEEE International Symposium on Circuits and Systems (ISCS)

Symposium on VLSI Circuits

Symposium on VLSI Technology

International Symposium on Low Power Electronics and Design (ISLPED)

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)

Design, Automation and Test in Europe (DATE’2007)

IEEE Asia Pacific Conference on Circuits and Systems

国外会议介绍

1 DAC 2005

会议名称： the 42nd Design Automation Conference

时间/地点： June 13-17, 2005, Anaheim, California,

截稿时间： Nov. 3, 2004

相关网址： http://www.dac.com/42nd/index.html

论文范围：

􀁺 system level design methodology

􀁺 embedded and real-time systems

􀁺 behavioral/logic synthesis and optimization

􀁺 validation and verification for behavioral/logic design

􀁺 circuit optimization and simulation

􀁺 physical design and interconnect optimization

􀁺 test and design for testability

􀁺 analog and RF circuit design

􀁺 design for manufacturability and TCAD

􀁺 reconfigurable systems

􀁺 leading-edge designs

2 ICCAD 2005

会议名称： International Conference on Computer Aided Design

时间/地点： November 6-10, 2005

截稿时间： April 20, 2005

相关网址： http://www.iccad.com/

论文范围：

1) physical design and test

2) synthesis and system design

3) verification, modeling and simulation

4) innovative design technologies for devices, circuits and systems

3 PATMOS 2005

会议名称： Power and Timing Modeling, Optimization and Simulation

时间/地点： 21-23 Sep 2005, Leuven, Belgium

截稿时间： 31 March 2005

相关网址： http://www.imec.be/patmos/

论文范围：

The objective of the workshop is to provide a forum to discuss and investigate the

emerging problems in the design methodologies and CAD-tools for the new generation

of IC technologies. A major emphasis of the technical program is on speed and

low-power aspects with particular regards to modeling, characterization, design and

architectures

该会议论文一般由SCI 收录！

4 ASICON 2005

会议名称： The 6th International Conference On ASIC

时间/地点： October 17-20, 2005, Shanghai, China

截稿时间： April 30, 2005（该会议论文一般由SCI 收录！）

相关网址： http://www.asicon2005.com/

论文范围：

[1] VLSI Design

[2] VLSI circuits

[3] Analog, mixed signal and RF circuit design

[4] Testing technology and design for testability

[5] Programmable devices

[6] Physical design

[7] Synthesis and system design, verification

[8] Modeling and simulation

Other VLSI Design related topics.

5 ISPD 2005

会议名称： ACM International Symposium on Physical Design

时间/地点： April 3-6,2005 San Francisco ,CA

截稿时间： October 17, 2004（该会议每年一次，本信息仅供参考！）

相关网址： http://www.ispd.cc/

论文范围：

􀁺 Floor planning and interconnect planning

􀁺 Interactions with behavior-level synthesis flows

􀁺 Partitioning, placement and routing

􀁺 Interactions with logic-level (re-)synthesis flows

􀁺 Compaction and layout verification, Analysis and management of power dissipation

􀁺 Synthesis optimizations within physical design,

􀁺 Management of design data and constraints

􀁺 Estimation and modeling New physical design methodologies

􀁺 Timing and crosstalk issues in physical design New paradigms in physical design

􀁺 Physical design for manufacturability and yield

􀁺 Design for large and/or high-performance systems

􀁺 Special structures for clocking and power networks

􀁺 Circuit performance measurements in a PD context

􀁺 Physical design in parallel/ distributed/Web environments

6 CICC 2005

会议名称： The IEEE Custom Integrated Circuits Conference

时间/地点： September 18 - 21, 2005，DoubleTree Hotel, San Jose, California

截稿时间： 18 Apr 2005

相关网址： http://www.ieee-cicc.org/home.html

论文范围：

􀁺 Analog Circuit Design

􀁺 Custom Applications and Low-Power Techniques

􀁺 Signal and Data Processing

􀁺 Embedded Memory

􀁺 Emerging Technologies

􀁺 Programmable Devices

􀁺 Simulation-Modeling

􀁺 SoC/SiP- IP Generation and Management

􀁺 Test, Debug, and Reliability

7 ESSCIRC 2005

会议名称： 31ts European Solid-State Circuits Conference

时间/地点： 2005-9-12, Grenoble , France

截稿时间： 2005-4-9

相关网址： www.esscirc2005.com

论文范围：

Analogue circuits, Digital circuits, RF communication circuits

Mixed signal circuits and Microsystems, Data converters

8 CAD/Graphics 2005

会议名称： The 9th International CAD/Graphics 2005 conference

时间/地点： December 7-10, 2005, Hong Kong，China

截稿时间： May 31, 2005

相关网址： http://conference.ieem.ust.hk/~cadcg05/cfp.htm

论文范围：

–Geometric, solid and heterogeneous modeling

–Computer animation

–Rendering techniques

–Computer graphics systems and hardware

–Computer graphics in Arts, Education, Engineering, Entertainment

–Scientific computing and visualization

–Large discredited models

–Image based modeling and rendering, computer vision

–Multimedia

–CAD data bases, data exchange and standards

–Virtual reality, computer human interface

–Applications of computational geometry

–Numerical control algorithms

–Design computing, AI in design

–Computer Aided IC Design

–Geometric and engineering tolerances

9 CSS 2005

会议名称： The 3rd IASTED International Conference on Circuits, Signals, and Systems

时间/地点： October 24-26, 2005，Marina del Rey, CA, USA

截稿时间： May 15, 2005（该会议每年一次，仅供参考！）

相关网址： http://www.iasted.org/conferences/2005/marina/c493.htm

论文范围： Digital Circuits and Systems, Integrated Circuits

RF and High-frequency Circuits, VLSI Circuits and Systems, Systems on a Chip

Nonlinear Circuits and Systems, Optoelectronic Circuits, Power Electronics

Nanotechnology, Computer-aided Design, Biologically Inspired Circuits and Systems

Communication Circuits and Systems, Robotics, Digital Signal Processing

Image Processing, Pattern Recognition, Visualization, Speech Processing

Communication Systems, Wireless Communication, Multimedia

Control Theory, Control Systems, Fuzzy Logic, 等

10 ASYNC 2005

会议名称： the 11th IEEE International Symposium on Asynchronous Circuits and Systems

时间/地点： March 13-16, 2005, New York City, USA

截稿时间： October 4, 2004

相关网址： http://vlsi.cornell.edu/async2005/

论文范围：

􀁺 Mixed synchronous/asynchronous architectures, interfaces, and circuits

􀁺 High-speed/low-power asynchronous logic, memories, and interconnects

􀁺 High-level design and synthesis of self-timed circuits

􀁺 Physical design of unclocked logic and pipelines

􀁺 Formal methods for correctness and performance analysis of asynchronous designs

􀁺 Test, reliability, security, and radiation tolerance

􀁺 CAD for asynchronous design and validation,

􀁺 Asynchronous System-on-a-chip (SoC)

􀁺 Novel asynchronous architectures

􀁺 Asynchrony and latency tolerance in system-level design

11 DATE 2005

会议名称： The 8th Design Automation and Test Conference in Europe

时间/地点： March 7 – 11, 2005 ICM, Munich, Germany

截稿时间： Sept. 12, 2004（该会议每年一次，本信息仅供参考！）

相关网址： http://www.date-conference.com/

论文范围：

􀁺 System Design Methods and Case Studies

􀁺 Analogue and Mixed A/D Systems

􀁺 Design of Low-Power Systems and Case Studies

􀁺 Platform Design and VC Reuse Methods

􀁺 System-Level Specification and Modelling

􀁺 Simulation and Emulation

􀁺 System Synthesis and Optimisation

􀁺 Architectural Synthesis

􀁺 Logic and FSM Synthesis

􀁺 Physical Design and Verification

􀁺 Defect-Based Testing and Test of Special Architectures

􀁺 SoC/SoB Test and Test Resource Partitioning

􀁺 Real-Time Systems

􀁺 Embedded Software Technology

􀁺 Media Processing

􀁺 Wireless Communication and Networking

􀁺 Data Storage and Control

􀁺 IP and Re-use

12 EDP 2005

会议名称： Electronic Design Processes Workshop 2005

时间/地点： April 7,8, 2005, Monterey California

截稿时间： February 10, 2005

相关网址： http://www.eda.org/edps/

论文范围：

Best practices and experiences

􀁺 Domain-specific methodologies: SOC, analog / mixed-signal, RF

􀁺 Metrics, Cost, time-to-market, productivity

􀁺 Scaling and migration

􀁺 Co-evolution of methodology and process technology

Human issues

􀁺 Large/distributed design teams，Manufacturing integration

􀁺 Process/device characterization, modeling

􀁺 Functional verification，HW/SW co-design，IP reuse

􀁺 Future methodology needs and concepts

􀁺 Impact of design-manufacturing interface

􀁺 Process advances and multi-technology integration

􀁺 New tool/algorithms

13 DDECS 2005

会议名称： IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 2005

时间/地点： April 13-16, 2005, Sopron, Hungary

截稿时间： January , 2005（该会议每年一次，本信息仅供参考！）

相关网址： http://sauron.inf.mit.bme.hu/DDECS05.nsf

论文范围：

􀁺 Analog, Mixed-Signal and RF Test, ASIC/FPGA Design,

􀁺 ATE Hardware and Software

􀁺 Bio-inspired Hardware, Built-in Self-Test (BIST),

􀁺 Defect/Fault Tolerance and Reliability, Design Verification/Validation

􀁺 Design for Testability and Diagnosis, Embedded Test,

􀁺 Formal Methods in System Design, Hardware/Software Co-Design, IP-based Design

􀁺 Logic Synthesis, Memory and Processor Test, MEMS Testing, Physical Design

􀁺 Reconfigurable Computing, System-on-a-Chip (SoC)

14 ASP-DAC 2006

会议名称： 11th Asia and South Pacific Design Automation Conference

时间/地点： Jan. 24-27，2006 Yokohama City, Japan

截稿时间： July 20, 2005

相关网址： http://www.aspdac.com/aspdac2006/

论文范围：

[1] System Level Design Methodology

[2] Embedded and Real-Time Systems

[3] Behavioral/Logic Synthesis and Optimization

[4] Validation and Verification for Behavioral/Logic Design

[5] Physical Design

[6] Timing, Power, Signal/Power Integrity Analysis and Optimization

[7] Interconnect, Device and Circuit Modeling and Simulation

[8] Test and Design for Testability

[9] Analog, RF and Mixed Signal Design and CAD

[10] Leading Edge Design Methodology for SOCs and SIPs

15 SASIMI 2006

会议名称： The 13th Workshop on Synthesis and System Integration of Mixed Information

Technologies

时间/地点： Apr. 3-4, 2006, Nagoya, Japan

截稿时间： November 11, 2005

相关网址： http://www.sasimi.jp

论文范围：

Layout/Logic/Behavioral Synthesis Test, Verification and Simulation System Design and

Design Experiences Embedded Software Design and HW/SW Co-design Analog and

Mixed-Signal Design New Design Methodologies (Reconfigurable Systems, MEMS,

etc.)

16 VLSI 2005

会议名称： 13th IFIP International Conferences on Very Large Scale Integration

时间/地点： October 17-19,2005 Perth, Western Australia

截稿时间： March 28, 2005

相关网址： http://vlsi2005.ecu.edu.au/

论文范围：

􀁺 Analog and Mixed-Signal IC Design, Digital IC Design, Physical Design

􀁺 Digital Signal Processing and Image Processing IC Design

􀁺 Telecommunication Circuits and Applications

􀁺 Special and Reconfigurable ("Soft-Hardware") Architectures

􀁺 Hardware Reconfiguration (FPGA-based circuits, systems and applications)

􀁺 Systems on Chip (embedded systems, IPs, ...)

􀁺 Opto-ULSI processing, Modelling and Simulation

􀁺 Deep Submicron Design and Modelling Issues

􀁺 Micromechanical Systems

􀁺 Verification, Low-Power Design, Logic and High-Level Synthesis

􀁺 Prototyping and Validation, Testability and Design for Test, CAD/CAE tools

17 ISLPED 2005

会议名称： International Symposium on Low Power Electronics and Design

时间/地点： August 8-10,2005, San Diego, California

截稿时间： February 20, 2005（该会议每年一次，仅供参考！）

相关网址： http://eeserver.ee.virginia.edu/~islped/

论文范围：

1. Architecture, Circuits, and Technology

􀁺 Technologies and Digital Circuits, Emerging logic and memory technologies,

􀁺 Device design, Low leakage circuits, Memory circuits,

􀁺 Cooling technologies, Battery technologies

􀁺 Logic and Micro-architecture Design

􀁺 Logic and RTL design, Arithmetic and signal processing circuits

􀁺 Processor core design, Cache design,

􀁺 Temperature aware design, Asynchronous design

􀁺 Analog, MEMS and Mixed Signal Electronics, RF circuits, Wireless, MEMS

circuits, AD/DA, Converters, Mixed-signal circuits, DC-DC conversion

2. Design Tools, Systems and Software Design

􀁺 Energy estimation and optimization tools that operate at the circuit/gate level, RT

level, behavioral level, and algorithmic level, Physical design and interconnects

􀁺 System Design and Methodologies, Microprocessor and DSP-based systems

􀁺 Embedded systems design, SOC designs, Reconfigurable systems,

􀁺 System level power management and design aids

􀁺 Power aware compiler and operating system design,

􀁺 Application level optimizations, Wireless and sensor networks

18 Hot Chips 2005

会议名称： A Symposium on High-Performance Chips

时间/地点： Aug 14-16，2005, Palo Alto, USA

截稿时间： 25 March 2005