How to Run Co-Simulation Using Hsim/Verilog
INDEX
1.Introduction
2.Known Limitation of the Nassda/Cadence Flow
3.Hsim/Verilog Co-Sim Usage
3.1 Setup the Co-Sim Environment
3.2 Setup Co-Sim Configuration File
3.3 Co-Sim with Verilog as the Top Instance
3.4 Co-Sim with Spice as the Top Instance
4.Cadence Analog Design Environment Integration
5.Reference
1.Introduction
This digital co-simulation (Co-Sim) solution is the integration between the Hsim circuit simulator and Cadence's Verilog simulators (NC-Sim/NC-Verilog/Verilog-XL). This integration is based on the standard Verilog PLI 2.0.
[Applications]
-The most frequent application is the block-level debug of an analog or mixed-signal block in conjunction with its surrounding digital circuitry represented by Verilog or VHDL RTL code.
-Sometimes an existing Verilog testbench is used to drive an Hsim simulation of a design at the transistor-level.
-Another application is the top-level verification of a huge digital design (a processor for example) which requires a lot of digital patterns and a sensitive mixed-signal block is simulated in Hsim.
Setting up this co-simulation usually takes less than 2 hours, starting from scratch to get to the first simulation results. If the majority of the design is being simulated in the Verilog simulator and the remainder in Hsim, then speed-ups of 5X or more are possible compared to an all-transistor simulation in Hsim.
2.Known Limitation of the Nassda/Cadence Flow
The Nassda Co-Sim solution accepts both Verilog and SPICE format netlist descriptions on top. The management of the interface nodes is straightforward and the analog-to-digital (a2d) and digital-to-analog (d2a) signal converters are created automatically.
It is possible to let the digital simulator run for a while before starting the co-simulation with Hsim. This is typically useful to reach a state that could require a long setup time.
On the digital side, this solution doesn't currently support VHDL on top. However, it is generally possible to embed the VHDL code in a Verilog module to overcome this limitation.
Some care needs to be taken in deciding the partition of the design into analog and digital portions. Tight feedback loops that work across the interface between the two simulators can cause the analysis to be slower than expected. Choose partitions that have minimal signal traffic among them. This allows the digital engine to work quickly without being restrained by the possibly slower speed of the analog engine.
3.Hsim/Verilog Co-Sim Usage
3.1 Setup the Co-Sim Environment
Set NC -Verilog executable path — Make sure that the NC-Verilog software is installed and add the NC-Verilog executable path to PATH:
set path=($path /usr/local/vendors/cadence/ldv40/tools/bin)
Set LD_LIBRARY_PATH — Add library path to LD_LIBRARY_PATH (or SHLIB_PATH for HP):
setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH} :/usr/local/vendors/cadence/ldv40/tools/inca/lib:/usr/local/vendors/cadence/ldv40/tools/lib
Set Co-Sim Library libvpiHsim.so or .sl — Make sure that the Co-Sim software is installed. The shared library libvpiHsim.so or .sl must be present in the correct:
$NASSDA_HOME/platform/[correct OS]/bin path
Set TCL_LIBRARY — Set environment variable TCL_LIBRARY to the directory containing the init.tcl file:
setenv TCL_LIBRARY $NASSDA_HOME/etc/tcl
If your installed TCL is not version 8.4, then you can use either the Cadence installation tree:
setenv TCL_LIBRARY /soft/cadence/ldv40/tools/txe/lib/tcl8.3
Or the previous Nassda installation tree:
setenv TCL_LIBRARY .../nassda2.0/etc/tcl
3.2 Setup Co-Sim Configuration File
The file cosim.cfg, defines the spice netlist and the different parameters for the co-simulation.
Define the spice netlist name — Using the following command:
set_args -spectre test.sp -o run1 /* using spice deck in spectre syntax */
set_args test.sp /* using spice deck in default spice syntax */
Define the a2d & d2a params (if needed) — In most cases, the default a2d and d2a parameters (slopes, threshold, max and min values) are sufficient.
set_port_prop -cell MBLOCK -port * -logichv 1.2 -logiclv 0 -logicxv 0.0 -slope 100ps -vhi 0.84 -vlo 0.36
3.3 Co-Sim with Verilog as the Top Instance
Typically, you have a circuit or testbench in Verilog, and you want to simulate one or several modules in spice.
Step 1 — Copy the port definition from the original Verilog module to a separate file. Add one system task $nsda_module() in the module body to designate this module to be simulated by Hsim. Usually, remove the rest of the body of the module to make it cleaner. Move the original .v file to another location so it will not be compiled in Step 3. For example:
module inv (a, z);
input a;
output z;
initial $nsda_module();
endmodul e
Step 2 — Prepare the spice netlist, it must contain:
a). The subckt definition to be simulated
b). The call to the different model libraries
c). .param hsimvdd=[value] sets maximum value for the a2d and d2a
d). .tran statement
e). .plot v(.) or .lprint to plot the required signals
f). The normal Hsim accuracy/speed settings
Step 3 — Compile the Verilog source files including the new interface module from Step 1.
ncvlog *.v
Step 4 — Perform the elaboration
ncelab -loadvpi libvpiHsim.so:nsda_vpi_startup -access +rwc -libname cosim_lib cosim_lib.top
Step 5 — Start the co-sim
For NC-Sim: ncsim -loadvpi libvpiHsim.so:nsda_vpi_startup +nsda +"cosim.cfg" top
For NC-Verilog: ncverilog +loadvpi="libvpiHsim".so:nsda_vpi_startup +nsda+"cosim.cfg" +access +rwc *.v
For Verilog-XL: verilog +loadvpi="libvpiHsim".so:nsda_vpi_startup +nsda+"cosim.cfg" *.v
3.4 Co-Sim with Spice as the Top Instance
Step 1 — Add two Hsim commands to spice netlist
.param Hsimvmod=[Verilog module name]
.param Hsimverilog=[Verilog file name]
Run Hsim with the new spice netlist. With the above two commands in the netlist, Hsim only generates the necessary interface files and does not do any DC or transient circuit analysis. This Hsim simulation creates both cosim.v and cosim.sp. Cosim.v is the Verilog top module to instantiate other Verilog modules for co-sim. Cosim.sp is the spice subcircuit with interface elements. Remove the previous two Hsim commands and include the generated file cosim.sp in the original SPICE netlist:
.include cosim.sp
Step 2 — The spice netlist must contain:
a) The top level definition to be simulated
b) The call to the different model libraries
c) .param hsimvdd= to set the maximum value for the a2d and d 2a
d) .tran statement
e) .plot v(.) or .lprint to plot the required signals
f) The normal Hsim speed/accuracy settings
Step 3 — Compile cosim.v with other Verilog source files with the command:
ncvlog *.v
Step 4 — Perform the elaboration:
ncelab -loadvpi libvpiHsim.so:nsda_vpi_startup -access +rwc -libname cosim_lib cosim_lib.top
Step 5 — Start co-sim from top module defined in cosim.v with the following command
For NC-Sim: ncsim -loadvpi libvpiHsim.so:nsda_vpi_startup +nsda +"cosim.cfg" top
For NC-Verilog: ncverilog +loadvpi="libvpiHsim".so:nsda_vpi_startup +nsda +"cosim.cfg" +access +rwc *.v
For Verilog-XL: verilog +loadvpi="libvpiHsim".so:nsda_vpi_startup +nsda+"cosim.cfg" *.v
4.Cadence Analog Design Environment Integration
The co-simulation solution is integrated into the Cadence Virtuoso analog design environment (Analog Artist). It supports the existing SpectreVerilog flow that designers are already using. It allows the user to select the blocks to be simulated with either a digital or analog simulator, through the hierarchy browser. The SPICE and digital netlists are generated automatically by the environment. The main purpose of this solution is to allow for larger or more complex designs to be simulated.
This integration allows you to use Hsim as a mixed mode simulator via the Cadence Artist interface.
5.Reference
[1] HSIMPLUS v5.0 User’s Manual, Original Release, pp27.1-27.31, Apr. 2004, Nassda Corporation.
[2] http://www.deepchip.com/items/0424-09.html
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