一个Verilog程序，仿真不出想要的结果，请高手指点

     程序如下，想要实现如下功能：FVAL为帧有效信号，LVAL为行有效信号，flag1,flag2分别为两个存储器的标志信号，flag1为0时，向第一个存储器中存入数据，为1时读取第一个存储器中的数据；flag2为第二个存储器的标志信号，功能同flag1。

 d[31:0]为输入的32位数据信号，通过FPGA存储到两个外部存储器中。r[31:0]为内部寄存器，D1[31:0],D2[31:0]为输出到两个存储器数据信号。rst为复位信号，STROBE为时钟信号，其它为存储器使能信号。

module  acquisition(FVAL,LVAL,d,STROBE,rst,addr1,addr2,WE1,WE2,CS1,CS2,
                   D1,D2);
        
         input FVAL,LVAL;
         input STROBE;
         input rst;
         input[31:0] d;
        
        
         output[3:0] WE1,WE2;
         output[3:0] CS1,CS2;
         output[16:0]addr1,addr2;
         output[31:0] D1,D2;

        reg OE1,OE2;
        reg[3:0] WE1,WE2;
        reg[3:0] CS1,CS2;
        reg[16:0] addr1,addr2;
        reg[31:0] D1,D2 ;
        reg[31:0]r ;//寄存数据
        reg flag1;
        reg flag2;

   
       
    always@(posedge STROBE or posedge rst)
      begin
       if(rst)
         begin
          D1<=32'b00000000000000000000000000000000;
          D2<=32'b00000000000000000000000000000000;
         end
       else if(flag1==0)
         D1[31:0]<=r[31:0];
       else if(flag2==0)
         D2[31:0]<=r[31:0];
      end

    always@(posedge STROBE or posedge rst)
      if(rst)
        begin
         r[31:0]<=32'b00000000000000000000000000000000;
        end
      else if(FVAL&&LVAL)
        begin
         r[31:0]<=d[31:0];
        end

  always@(posedge rst or posedge FVAL)
  begin
    @(posedge rst)
     begin
      flag2<=1;
      flag1<=0;
     end
    @(posedge FVAL)
     begin
      flag1<=~flag1;
      flag2<=~flag2;
     end
  end 
  
 
always@(posedge STROBE or posedge rst)
      begin
       if(rst)
         addr1<=17'd0;
       else if(FVAL&&LVAL&&(!flag1))
         addr1<=addr1+17'd1;
       else if(!FVAL)
         addr1<=0;
       else if(flag1)
         addr1<=addr1+17'd1;
      end

   always@(posedge STROBE or posedge rst)
     begin
       if(rst)
         addr2<=17'd0;
       else if(FVAL&&LVAL&&(!flag2))
         addr2<=addr2+17'd1;
       else if(!FVAL)
         addr2<=0;
       else if(flag2)
         addr2<=addr2+17'd1;
     end 

  
    always@(posedge STROBE or posedge rst)
      begin
       if(rst)
          begin
          CS1[3:0]<=4'b1111;
          CS2[3:0]<=4'b1111;
          WE1[3:0]<=4'b1111;
          WE2[3:0]<=4'b1111;
          end
       else if(FVAL&&LVAL&&(!flag1))
          begin
          CS1[3:0]<=4'b0000;
          WE1[3:0]<=4'b0000;
          end
       else if(FVAL&&LVAL&&(!flag2))
          begin
          CS2[3:0]<=4'b0000;
          WE2[3:0]<=4'b0000;
          end
      else if(!FVAL)
          begin
          CS1[3:0]<=4'b1111;
          CS2[3:0]<=4'b1111;
          WE1[3:0]<=4'b1111;
          WE2[3:0]<=4'b1111;
          end
   end
  endmodule   

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