作者：xdkui
基于FPGA实现并口EPP协议
用FPGA做图像处理算法时，经常需要传输大数据量的图像数据到FPGA或者从FPGA到PC。这样就需要简单快速的传输方法。单片机常用串口，但速度有限。并口是PC机基本配置，传输速度相对较快。且EPP协议时序比较简单，故本文基于FPGA用Verilog HDL实现并口EPP协议，与PC机通讯。
并口有SPP，EPP，ECP3种模式，具体区别就不说了。选用EPP模式。其特性，时序及PC机端的IO端口地址见附件里的资料（Interfacing the Enhanced Parallel Port）。下面为用有限状态机实现的EPP协议（epp.v）：
module EPP (EPP_Write0,EPP_Data,EPP_Interrupt,EPP_Wait,EPP_DataStrobe0,EPP_Reset0,EPP_AddressStrobe0,,clk24,rst,led);
//EPP interface signals
input EPP_Write0;
inout [7:0] EPP_Data;
output EPP_Interrupt;
output EPP_Wait;
input EPP_DataStrobe0;
input EPP_Reset0;
input EPP_AddressStrobe0;
//
input clk24;
input rst;
output led;
/******************** module regs define ***************************/
//regs related to EPP
reg EPP_Interrupt,EPP_Wait;
reg EPP_Write,EPP_DataStrobe,EPP_AddressStrobe,EPP_Reset;
reg [7:0] epp_dataout,epp_datain;
//internal regs
reg led;
reg [2:0] epp_state;
reg [7:0] cmd;//from epp address write
/********************** module constant define *****************/
//parameters EPP state parameter EPP_IDLE=3'b000,EPP_WAIT_ADDRREAD=3'b001,EPP_WAIT_ADDRWRITE=3'b010,
EPP_WAIT_DATAREAD=3'b011,EPP_WAIT_DATAWRITE=3'b100;
/********************* module internal logic ******************/
//并口输入进来的信号，需要同步。加入锁存器
always @ (posedge clk24)
begin
if(!rst)
EPP_Write<=1;
else
EPP_Write<=EPP_Write0;
end
always @ (posedge clk24)
begin
if(!rst)
EPP_DataStrobe<=1;
else
EPP_DataStrobe<=EPP_DataStrobe0;
end
always @ (posedge clk24)
begin
if(!rst)
EPP_AddressStrobe<=1;
else
EPP_AddressStrobe<=EPP_AddressStrobe0;
end
always @ (posedge clk24)
begin
if(!rst)
EPP_Reset<=1;
else
EPP_Reset<=EPP_Reset0;
end
//EPP state machine
always @ (posedge clk24)
begin
if(!rst )
begin
epp_state<=EPP_IDLE;
EPP_Interrupt<=0;
EPP_Wait<=0;
epp_dataout<=8'b0;
epp_datain<=8'b0;
cmd<=8'b0;
//SRAM_Addr<=20'b0;
sram_raddr<=20'b0;
sram_waddr<=20'd0;
end
else
case(epp_state)
EPP_IDLE:
begin
epp_state<=EPP_IDLE;
EPP_Wait<=0;
if(!EPP_AddressStrobe)
begin
if(EPP_Write)
begin//EPP address read
epp_dataout<=EPP地址读，这里是要从地址寄存器读取的数据;
EPP_Wait<=1;
epp_state<=EPP_WAIT_ADDRREAD;
end
else
begin//EPP address write cmd come from EPP address write
cmd<=EPP_Data;//EPP_Data为EPP地址寄存器写入的数据
EPP_Wait<=1;
epp_state<=EPP_WAIT_ADDRWRITE;
end
end
else if(!EPP_DataStrobe)
begin
if(EPP_Write)
begin//EPP data read
epp_dataout<=EPP数据读，这里是要从数据寄存器读取的数据;
EPP_Wait<=1;
epp_state<=EPP_WAIT_DATAREAD;
end
else
begin//EPP data write
epp_datain<=EPP_Data;//EPP数据写，是写入数据寄存器的数据
EPP_Wait<=1;
epp_state<=EPP_WAIT_DATAWRITE;
end
end
end
EPP_WAIT_ADDRREAD:
begin
if(EPP_AddressStrobe)
begin
EPP_Wait<=0;
//led<=~led;
epp_state<=EPP_IDLE;
end
end
EPP_WAIT_ADDRWRITE:
begin
if(EPP_AddressStrobe)
begin
EPP_Wait<=0;