标签：
FPGA VHDL
2-4译码器的程序作为初步调试使用。
library IEEE;
use IEEE.Std_logic_1164.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;
architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch;
文档不是自己写的，来自网络，文档里面有出处和广告，我这里就不注明了。
系统分类:
CPLD/FPGA | 用户分类:
FPGA | 来源:
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