标签：
FPGA VHDL LED 1秒定时
程序思路很简单，就是利用50MHz的外部时钟输入，经过2次分频得到1秒的精确定时，给LED取反。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity led is
port(led1,led2,led3,led4:out bit;clk:in bit);
end led;
architecture led_blink of led is
begin
process(clk)
variable s1:integer:=0;
variable s2:integer:=0;
begin
i1:if (clk'event and clk='1') then
s1:=s1+1;
if(s1>20000) then
s2:=s2+1;
if(s2>2500 and s2<5000) then
led1<='1';
led2<='0';
led3<='1';
led4<='0';
elsif(s2>=5000) then
led1<='0';
led2<='1';
led3<='0';
led4<='1';
s2:=0;
end if;
s1:=0;
end if;
end if i1;
end process;
end led_blink;
系统分类:
CPLD/FPGA | 用户分类:
FPGA | 来源:
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