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library ieee ;
use ieee.std_logic_1164.all;
entity lamp is
port (nrst : in std_logic; --negative
shift_direction:in std_logic;--'1' for right ; '0' for left
clk:in std_logic;
Q : out std_logic_vector(7 downto 0) --controll 8 led lamp
);
end lamp;
architecture lamp of lamp is
signal temp : std_logic_vector(7 downto 0);
begin
process(clk,nrst,shift_direction)
begin
if nrst='0' then
temp(7 downto 0) <="10000000";
elsif clk'event and clk = '1' then
if shift_direction = '1' then
temp(7 downto 0) <= temp(0) & temp(7 downto 1) ;
else
temp(7 downto 0) <= temp(6 downto 0) & temp(7);
end if;
end if;
q(7 downto 0)<=temp(7 downto 0);
end process;
end lamp;
系统分类:
CPLD/FPGA | 用户分类:
VHDL/FPGA学习 | 来源:
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